DSPIC33FJ128MC708A-E/PT Microchip Technology, DSPIC33FJ128MC708A-E/PT Datasheet - Page 24

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DSPIC33FJ128MC708A-E/PT

Manufacturer Part Number
DSPIC33FJ128MC708A-E/PT
Description
16 Bit MCU/DSP 40MIPS 128KB FLASH 80 TQFP 12x12x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ128MC708A-E/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ128MC708A-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC33FJXXXMCX06A/X08A/X10A
2.7
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < F
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration Word.
2.8
If the MPLAB ICD 2, ICD 3 or REAL ICE in-circuit
emulator is selected as a debugger, it automatically
initializes all of the A/D input pins (ANx) as “digital” pins
by setting all bits in the AD1PCFGL register.
DS70594B-page 24
Oscillator Value Conditions on
Device Start-up
Configuration of Analog and
Digital Pins During ICSP
Operations
IN
< 8 MHz to comply with device PLL
Preliminary
The bits in this register that correspond to the A/D pins
that are initialized by the MPLAB ICD 2, ICD 3 or REAL
ICE in-circuit emulator, must not be cleared by the user
application firmware; otherwise, communication errors
will result between the debugger and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFGL register during initialization of the ADC
module.
When the MPLAB ICD 2, ICD 3 or REAL ICE in-circuit
emulator is used as a programmer, the user application
firmware must correctly configure the AD1PCFGL
register. Automatic initialization of this register is only
done during debugger operation. Failure to correctly
configure the register(s) will result in all A/D pins being
recognized as analog input pins, resulting in the port
value being read as a logic ‘0’, which may affect user
application functionality.
2.9
Unused I/O pins should be configured as outputs and
driven to a logic low state.
Alternatively, connect a 1k to 10k resistor to V
unused pins and drive the output to logic low.
Unused I/Os
 2009 Microchip Technology Inc.
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