DSPIC33FJ128MC708A-E/PT Microchip Technology, DSPIC33FJ128MC708A-E/PT Datasheet - Page 65

• Manufacturer Part Number: DSPIC33FJ128MC708A-E/PT
• Description: 16 Bit MCU/DSP 40MIPS 128KB FLASH 80 TQFP 12x12x1mm TRAY
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC708A-E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.2.7
In addition to its use as a working register, the W15
register in the dsPIC33FJXXXMCX06A/X08A/X10A
devices is also used as a software Stack Pointer. The
Stack Pointer always points to the first available free
word and grows from lower to higher addresses. It
pre-decrements for stack pops and post-increments for
stack pushes, as shown in Figure 4-6. For a PC push
during any CALL instruction, the MSb of the PC is
zero-extended before the push, ensuring that the MSb
is always clear.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM<0> is forced to ‘0’
because all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap will not occur. The stack error trap will occur on a
subsequent push operation. Thus, for example, if it is
desirable to cause a stack error trap when the stack
grows beyond address 0x2000 in RAM, initialize the
SPLIM with the value 0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-6:
 2009 Microchip Technology Inc.
0x0000
Note:
15
000000000
SOFTWARE STACK
A PC push during exception processing
concatenates the SRL register to the MSb
of the PC prior to the push.
<Free Word>
PC<15:0>
PC<22:16>
CALL STACK FRAME
dsPIC33FJXXXMCX06A/X08A/X10A
0
POP : [--W15]
PUSH : [W15++]
W15 (before CALL)
W15 (after CALL)
Preliminary
4.2.8
The
support data RAM protection features which enable
segments of RAM to be protected when used in con-
junction with Boot and Secure Code Segment Security.
BSRAM (Secure RAM segment for BS) is accessible
only from the Boot Segment Flash code when enabled.
SSRAM (Secure RAM segment for RAM) is accessible
only from the Secure Segment Flash code when
enabled. See Table 4-1 for an overview of the BSRAM
and SSRAM SFRs.
4.3
The addressing modes in Table 4-36 form the basis of
the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
4.3.1
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first
8192 bytes of data memory (Near Data Space). Most
file register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.3.2
The 3-operand MCU instructions are of the following
form:
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (i.e., the
addressing mode can only be Register Direct) which is
referred to as Wb. Operand 2 can be a W register
fetched from data memory or a 5-bit literal. The result
location can be either a W register or a data memory
location.
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-Bit or 10-Bit Literal
Note:
dsPIC33FJXXXMCX06A/X08A/X10A
Instruction Addressing Modes
The
DATA RAM PROTECTION FEATURE
FILE REGISTER INSTRUCTIONS
MCU INSTRUCTIONS
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
following
addressing
DS70594B-page 65
modes
devices
are