16-bit DSC, 128KB Flash,Motor,CAN,DMA,40 MIPS,nanoWatt 28 QFN-S 6x6mm T/R

DSPIC33FJ128MC802T-I/MM

Manufacturer Part NumberDSPIC33FJ128MC802T-I/MM
Description16-bit DSC, 128KB Flash,Motor,CAN,DMA,40 MIPS,nanoWatt 28 QFN-S 6x6mm T/R
ManufacturerMicrochip Technology
SeriesdsPIC™ 33F
DSPIC33FJ128MC802T-I/MM datasheets
 

Specifications of DSPIC33FJ128MC802T-I/MM

Core ProcessordsPICCore Size16-Bit
Speed40 MIPsConnectivityCAN, I²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDTNumber Of I /o21
Program Memory Size128KB (128K x 8)Program Memory TypeFLASH
Ram Size16K x 8Voltage - Supply (vcc/vdd)3 V ~ 3.6 V
Data ConvertersA/D 6x10b/12bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case28-QFN
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size-Other namesDSPIC33FJ128MC802T-I/MMTR
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2
6. Module: I
C
2
If there are two I
C devices on the bus, one of
them is acting as the Master receiver and the other
as the Slave transmitter. If both devices are
configured for 10-bit Addressing mode, and have
the same value in the A10 and A9 bits of their
addresses, then when the Slave select address is
sent from the Master, both the Master and Slave
acknowledge it. When the Master sends out the
read operation, both the Master and the Slave
enter into Read mode and both of them transmit
the data. The resultant data will be the ANDing of
the two transmissions.
Work around
2
In all I
C devices, the addresses as well as bits
A10 and A9 should be different.
Affected Silicon Revisions
A1
A2
A3
A4
X
X
X
X
2
7. Module: I
C
2
When the I
C module is configured as a 10-bit
slave with and address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather
than
0x02;
however,
acknowledges both address bytes.
Work around
None.
Affected Silicon Revisions
A1
A2
A3
A4
X
X
X
X
2
8. Module: I
C
2
With the I
C module enabled, the PORT bits and
external
interrupt
input
functions
associated with the SCL and SDA pins do not
reflect the actual digital logic levels on the pins.
Work around
If the SDA and/or SCL pins need to be polled,
these pins should be connected to other port pins
in order to be read correctly. This issue does not
2
affect the operation of the I
C module.
Affected Silicon Revisions
A1
A2
A3
A4
X
X
X
X
© 2010 Microchip Technology Inc.
9. Module: I
In 10-bit Addressing mode, some address
matches do not set the RBF flag or load the
receive register I2CxRCV, if the lower address
byte
matches
particular, these include all addresses with the
form XX0000XXXX and XX1111XXXX, with the
following exceptions:
• 001111000X
• 011111001X
• 101111010X
• 111111011X
Work around
Ensure that the lower address byte in 10-bit
Addressing mode does not match any 7-bit
reserved addresses.
Affected Silicon Revisions
A1
A2
X
X
10. Module: I
When the I
or Slave mode, after the ACKSTAT bit is set when
the
module
receiving a NACK, it may be cleared by the
reception of a Start or Stop bit.
Work around
Store the value of the ACKSTAT bit immediately
after receiving a NACK from the master.
Affected Silicon Revisions
A1
A2
X
X
11. Module: UART
The UART error interrupt may not occur, or may
(if
any)
occur at an incorrect time, if multiple errors occur
during a short period of time.
Work around
Read the error flags in the UxSTA register
whenever a byte is received to verify the error
status. In most cases, these bits will be correct,
even if the UART error interrupt fails to occur.
Affected Silicon Revisions
A1
A2
X
X
2
C
the
reserved
addresses.
In
A3
A4
X
X
2
C
2
C module is operating in either Master
A3
A4
X
X
A3
A4
X
X
DS80442F-page 5