16-bit DSC, 128KB Flash,Motor,CAN,DMA,40 MIPS,nanoWatt 28 QFN-S 6x6mm T/R

DSPIC33FJ128MC802T-I/MM

Manufacturer Part NumberDSPIC33FJ128MC802T-I/MM
Description16-bit DSC, 128KB Flash,Motor,CAN,DMA,40 MIPS,nanoWatt 28 QFN-S 6x6mm T/R
ManufacturerMicrochip Technology
SeriesdsPIC™ 33F
DSPIC33FJ128MC802T-I/MM datasheets
 


Specifications of DSPIC33FJ128MC802T-I/MM

Core ProcessordsPICCore Size16-Bit
Speed40 MIPsConnectivityCAN, I²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDTNumber Of I /o21
Program Memory Size128KB (128K x 8)Program Memory TypeFLASH
Ram Size16K x 8Voltage - Supply (vcc/vdd)3 V ~ 3.6 V
Data ConvertersA/D 6x10b/12bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case28-QFN
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size-Other namesDSPIC33FJ128MC802T-I/MMTR
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12. Module: UART
When the UART is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA encoder/decoder
(IREN = 1), the module incorrectly transmits a data
payload of 80h as 00h.
Work around
None.
Affected Silicon Revisions
A1
A2
A3
A4
X
X
X
X
13. Module: Comparator
If CMCON<CxOUTEN> bit is set and the
comparator
module
CMCON<CxEN>
disabled, the remappable comparator output pins,
C1OUT and C2OUT, cannot be used as general
purpose I/O pins.
Work around
When the comparator module is disabled the
CMCON<CxOUTEN> bit should be reset so that
the remappable comparator output pins C1OUT
and C2OUT are not driven onto the output pad.
Affected Silicon Revisions
A1
A2
A3
A4
X
X
X
X
14. Module: Internal Voltage Regulator
When the VREGS bit (RCON<8>) is set to a logic
‘0’, the device may reset and a higher Sleep
current may be observed.
Work around
Ensure VREGS bit (RCON<8>) is set to a logic ‘1’
for device Sleep mode operation.
Affected Silicon Revisions
A1
A2
A3
A4
X
X
X
X
DS80442F-page 6
15. Module: PSV Operations
An address error trap occurs in certain addressing
modes when accessing the first four bytes of an
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register Indirect Addressing (Word or Byte
mode) with pre/post-decrement
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum.
bit
is
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 tool suite for further details.
Affected Silicon Revisions
A1
A2
A3
X
X
X
16. Module: ECAN
The WAKIF bit in the CxINTF register cannot be
cleared by software instruction after the device is
interrupted from Sleep due to activity on the CAN
bus.
When the device wakes up from Sleep due to CAN
bus activity, the ECAN module is placed in
operational mode. The ECAN Event interrupt
occurs due to the WAKIF flag. Trying to clear the
flag in the Interrupt Service Routine (ISR) may not
clear the flag. The WAKIF bit being set will not
cause
repetitive
execution.
Work around
Although the WAKIF bit does not clear, the device
Sleep and ECAN Wake function continue to work
as expected. If the ECAN event is enabled, the
CPU will enter the Interrupt Service Routine due to
the WAKIF flag getting set. The application can
maintain a secondary flag, which tracks the device
Sleep and Wake events.
Affected Silicon Revisions
A1
A2
A3
X
X
X
A4
X
Interrupt
Service
Routine
A4
X
© 2010 Microchip Technology Inc.