DSPIC33FJ128MC802T-I/MM Microchip Technology, DSPIC33FJ128MC802T-I/MM Datasheet - Page 8

16-bit DSC, 128KB Flash,Motor,CAN,DMA,40 MIPS,nanoWatt 28 QFN-S 6x6mm T/R

DSPIC33FJ128MC802T-I/MM

Manufacturer Part Number
DSPIC33FJ128MC802T-I/MM
Description
16-bit DSC, 128KB Flash,Motor,CAN,DMA,40 MIPS,nanoWatt 28 QFN-S 6x6mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC802T-I/MM

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ128MC802T-I/MMTR
22. Module: UART
23. Module: QEI
24. Module: QEI
EXAMPLE 1:
DS80442F-page 8
AD1CON1bits.ADON = 0;
__asm__ volatile ("REPEAT #50");
__asm__ volatile ("NOP");
Sleep();
The UART module will not generate consecutive
break characters. Trying to perform a back-to-back
Break character transmission will cause the UART
module to transmit the dummy character used to
generate the first Break character instead of
transmitting the second Break character. Break
characters are generated correctly if they are
followed by non-Break character transmission.
Work around
None.
Affected Silicon Revisions
When the TQCS and TQGATE bits in the
QEIxCON register are set, a QEI interrupt should
be generated after an input pulse on the QEA
input. This interrupt is not generated in the affected
silicon.
Work around
None.
Affected Silicon Revisions
When the TQCS and TQGATE bits in the
QEIxCON register are set, the POSCNT counter
should not increment but erroneously does, and if
allowed to increment to match MAXCNT, a QEI
interrupt will be generated.
Work around
To prevent the erroneous increment of POSCNT
while
Accumulation mode, initialize MAXCNT = 0.
Affected Silicon Revisions
A1
A1
A1
X
X
X
A2
A2
running
A2
X
X
X
A3
A3
A3
X
X
X
the
A4
A4
A4
X
X
X
QEI
in
Timer
//Disable the ADC module
//Wait 50 Tcy
//Repeat NOP 51 times
// Execute PWRSAV #0 and go to Sleep
Gated
25. Module: Audio DAC
26. Module: ADC
Note:
Note:
The Audio DAC positive differential output voltage
and
(parameters DA01 and DA02, respectively) may
not meet the specifications listed in the data sheet.
Work around
None.
Affected Silicon Revisions
If the ADC module is in an enabled state when the
device enters Sleep mode as a result of executing
a PWRSAV #0 instruction, the device power-down
current (I
in the device data sheet. This may happen even if
the ADC module is disabled by clearing the ADON
bit prior to entering Sleep mode.
Work around 1:
In order to remain within the I
listed in the device data sheet, the user software
must completely disable the ADC module by
setting the ADC Module Disable bit in the
corresponding Peripheral Module Disable register
(PMDx), prior to executing a PWRSAV
instruction.
Work around 2:
If the ADC module was previously initialized and
enabled, before entering Sleep, execute the lines
of code provided in
Affected Silicon Revisions
A1
A1
X
X
negative
The ADC module must be reinitialized by
the user application before resuming ADC
operation.
Unlike
application does not need to reinitialize
the ADC module; however, it is necessary
to re-enable the ADC module by setting
the ADON bit after waking from Sleep.
A2
A2
X
X
PD
) may exceed the specifications listed
A3
A3
X
X
Work
differential
© 2010 Microchip Technology Inc.
Example
A4
A4
X
around
1.
PD
output
1,
specifications
the
voltage
user
#0

Related parts for DSPIC33FJ128MC802T-I/MM