DSPIC33FJ16MC101T-I/SS Microchip Technology, DSPIC33FJ16MC101T-I/SS Datasheet
DSPIC33FJ16MC101T-I/SS
Specifications of DSPIC33FJ16MC101T-I/SS
Related parts for DSPIC33FJ16MC101T-I/SS
DSPIC33FJ16MC101T-I/SS Summary of contents
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... High-Performance, Ultra Low Cost © 2011 Microchip Technology Inc. 16-bit Digital Signal Controllers Preliminary Data Sheet DS70652C ...
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... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U ...
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... MIPS) = 488 Hz for Edge-Aligned mode, 244 Hz for Center-Aligned mode - PWM frequency for 11-bit resolution (@ 16 MIPS) = 15.63 kHz for Edge-Aligned mode, 7.81 kHz for Center-Aligned mode © 2011 Microchip Technology Inc. dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102 Power Management: • Single supply on-chip voltage regulator • ...
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... Shifts for up to 40-bit data • fractional multiply/divide operations Packaging: • 18-pin PDIP/SOIC • 20-pin PDIP/SOIC/SSOP • 28-pin SPDIP/SOIC/SSOP/QFN • 28-pin QFN: 6x6 mm • 36-pin TLA: 5x5 mm Note: See Table 1 features per device. Preliminary © 2011 Microchip Technology Inc. for the list of peripheral ...
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... The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102 CONTROLLER FAMILIES Device dsPIC33FJ16GP101 dsPIC33FJ16GP102 dsPIC33FJ16MC101 dsPIC33FJ16MC102 Note 1: Two out of three timers are remappable. 2: Two out of three interrupts are remappable. © 2011 Microchip Technology Inc. Remappable Peripherals — — — ...
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... Pins are tolerant DD SS (1) /CN11/RB15 (1) /CN12/RB14 CAP SS (1) /CN21/RB9 (1) /CN22/RB8 (1) /CN23/RB7 DD SS (1) /CN11/RB15 (1) /CN12/RB14 DD CAP SS (1) /CN21/RB9 (1) /CN22/RB8 (1) /CN23/RB7 DD SS (1) /CN11/RB15 (1) /CN12/RB14 (1) /CN13/RB13 (1) /CN14/RB12 (1) /CN15/RB11 (1) /CN16/RB10 CAP SS (1) /CN21/RB9 (1) /CN22/RB8 (1) /CN23/RB7 (1) /CN24/RB6 Table 1 for the list of available © 2011 Microchip Technology Inc. ...
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... FLTB1 /ASDA1/RP5 Note 1: The RPn pins can be used by any remappable peripheral. See peripherals. 2: The PWM Fault pins are enabled and asserted during any reset event. Refer to “PWM Faults” for more information on the PWM faults. © 2011 Microchip Technology Inc. MCLR ...
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... V externally. SS DS70652C-page (1) /CN4/RB0 1 (1) /CN5/RB1 2 (1) /CN6/RB2 3 dsPIC33FJ16GP102 (1) /CN7/RB3 OSCI/CLKI/CN30/RA2 Preliminary = Pins are tolerant 23 22 (1) RP13 /CN13/RB13 21 (1) RP12 /CN14/RB12 20 (1) RP11 /CN15/RB11 19 (1) RP10 /CN16/RB10 18 V CAP (1) SDA1/SDI1/RP9 /CN21/RB9 15 Table 1 for the list of available © 2011 Microchip Technology Inc. ...
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... The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally The PWM Fault pins are enabled and asserted during any reset event. Refer to “PWM Faults” for more information on the PWM faults. © 2011 Microchip Technology Inc (1) ...
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... V externally. SS DS70652C-page (1) /CN4/RB0 1 (1) /CN5/RB1 2 (1) /CN6/RB2 3 (1) /CN7/RB3 4 dsPIC33FJ16GP102 (1) /CN1/RB4 Preliminary = Pins are tolerant ( RP13 /CN13/RB13 (1) 26 RP12 /CN14/RB12 (1) 25 RP11 /CN15/RB11 (1) 24 RP10 /CN16/RB10 CAP N/C (1) SDA1/SDI1/RP9 /CN21/RB9 Table 1 for the list of available © 2011 Microchip Technology Inc. ...
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... The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to V externally The PWM Fault pins are enabled and asserted during any reset event. Refer to “PWM Faults” for more information on the PWM faults. © 2011 Microchip Technology Inc ...
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... Electrical Characteristics .......................................................................................................................................................... 247 27.0 Packaging Information.............................................................................................................................................................. 289 Appendix A: Revision History............................................................................................................................................................. 311 Index ................................................................................................................................................................................................. 315 The Microchip Web Site ..................................................................................................................................................................... 319 Customer Change Notification Service .............................................................................................................................................. 319 Customer Support .............................................................................................................................................................................. 319 Reader Response .............................................................................................................................................................................. 320 Product Identification System............................................................................................................................................................. 321 DS70652C-page 12 Preliminary © 2011 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com © 2011 Microchip Technology Inc. to receive the most current information on all of our products. Preliminary DS70652C-page 13 ...
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... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 14 Preliminary © 2011 Microchip Technology Inc. ...
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... Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ16GP101/ 102 and dsPIC33FJ16MC101/102 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2011 Microchip Technology Inc. and Reference and Preliminary DS70652C-page 15 ...
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... Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support MCLR OC/ UART1 ADC1 PWM1-2 IC1-IC3 CNx I2C1 Preliminary PORTA PORTB 16 Remappable Pins 16-bit ALU 16 RTCC PWM 6 Ch “Pin Diagrams” for the specific pins © 2011 Microchip Technology Inc. ...
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... The FLTB1 pin is not available on dsPIC33FJ16MC101 (20-pin) devices. 3: The PWM Fault pins are enabled during any reset event. Refer to information on the PWM faults. © 2011 Microchip Technology Inc. Description Analog input channels. External clock source input. Always associated with OSC1 pin function. ...
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... SS Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog = Analog input O = Output Preliminary internally Power I = Input Section 15.2 “PWM Faults” for more © 2011 Microchip Technology Inc. ...
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... Section 51. “Introduction (Part VI)” (DS70655) • Section 52. “Oscillator (Part VI)” (DS70644) • Section 53. “Interrupts (Part VI)” (DS70633) • Section 54. “Comparator with Blanking” (DS70647) • Section 55. “Charge Time Measurement Unit (CTMU)” (DS70635) © 2011 Microchip Technology Inc. web site 2 C™)” (DS70195) ...
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... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 20 Preliminary © 2011 Microchip Technology Inc. ...
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... Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 “External Oscillator © 2011 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS ...
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... Ensure that the MCLR pin V and V specifications are met MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V and V specifications are met © 2011 Microchip Technology Inc. is ...
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... REAL ICE™ In-Circuit Debugger User’s Guide” (DS51616) ® • “Using MPLAB REAL ICE™” (poster) (DS51749) © 2011 Microchip Technology Inc. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Configuration” ...
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... Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternately, connect 10k resistor between V and unused pins. DS70652C-page 24 SS Preliminary © 2011 Microchip Technology Inc. ...
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... As a result, three parameter instructions can be supported, allowing operations to be executed in a single cycle. © 2011 Microchip Technology Inc. A block diagram of the CPU is shown in the programmer’s model for the dsPIC33FJ16GP101/ 102 and dsPIC33FJ16MC101/102 is shown in Figure 3-2 ...
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... Data Latch Data Latch PCL X RAM Y RAM Address Address Loop Control Latch Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support Preliminary dsPIC33FJ16GP101/102 and 16-bit ALU 16 To Peripheral Modules © 2011 Microchip Technology Inc. ...
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... Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG OAB SAB DA SRH © 2011 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 PC0 0 Program Space Visibility Page Address ...
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... The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). DS70652C-page 28 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2011 Microchip Technology Inc. ...
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... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). © 2011 Microchip Technology Inc. (2) Preliminary DS70652C-page 29 ...
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... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70652C-page 30 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) Preliminary R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2011 Microchip Technology Inc. ...
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... The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. © 2011 Microchip Technology Inc. 3.6 DSP Engine and The DSP engine consists of a high-speed 17-bit x ...
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... AND dsPIC33FJ16MC101/102 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70652C-page 32 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill © 2011 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. © 2011 Microchip Technology Inc. 3.6.2.1 The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input. • ...
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... W13 as a 1.15 fraction. • [W13 Register Indirect with Post-Increment: The rounded contents of the non-target accumu- lator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write). Preliminary © 2011 Microchip Technology Inc. ...
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... MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. © 2011 Microchip Technology Inc. 3.6.3.2 In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator ...
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... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 36 Preliminary © 2011 Microchip Technology Inc. ...
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... FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102 DEVICES Note 1: On reset, these bits are automatically copied into the device configuration shadow registers. © 2011 Microchip Technology Inc. 4.1 Program Address Space The program dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/ and 102 devices is 4M instructions ...
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... Interrupt Service Routines (ISRs). A more detailed dis- cussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector least significant word (lsw Instruction Width Preliminary dsPIC33FJ16GP101/102 and devices reserve the Table”. PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2011 Microchip Technology Inc. ...
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... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2011 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so and care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...
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... Optionally Mapped into Program Memory 0xFFFF DS70652C-page 40 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x09FE 0x0A00 Y Data RAM (Y) 0x0BFE 0x0C00 0x1FFE 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space © 2011 Microchip Technology Inc. ...
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... X and Y address space also the X data prefetch path for the dual operand DSP instructions (MAC class). © 2011 Microchip Technology Inc. The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N, and MSC) to provide two concurrent data read paths ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED) SFR SFR Name Bit 15 Bit 14 Bit 13 Addr XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — Legend unknown value on Reset, — ...
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TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ16GP102 AND dsPIC33FJ16MC102 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 — CN30IE CN29IE — CNPU1 0068 CN15PUE CN14PUE CN13PUE ...
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TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — ...
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TABLE 4-6: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 4-9: 6-OUTPUT PWM1 REGISTER MAP FOR dsPIC33FJ116MC10X DEVICES SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P1TCON 01C0 PTEN — PTSIDL — P1TMR 01C2 PTDIR P1TPER 01C4 — P1SECMP 01C6 SEVTDIR PWM1CON1 01C8 — — — ...
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TABLE 4-11: UART1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — ...
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TABLE 4-13: ADC1 REGISTER MAP FOR dsPIC33FJ16GP102 AND dsPIC33FJ16MC102 DEVICES File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 ...
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TABLE 4-14: ADC1 REGISTER MAP FOR dsPIC33FJ16GP101 AND dsPIC33FJ16MC101 DEVICES File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0300 ADC1BUF0 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 ...
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TABLE 4-15: CTMU REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 CTMUCON1 033A CTMUEN — CTMUSIDL TGEN CTMUCON2 033C EDG2MOD EDG1POL EDG1SEL<3:0> CTMUICON 033E ITRIM<5:0> Legend unknown value on Reset, — = unimplemented, ...
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TABLE 4-18: COMPARATOR REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 CMSTAT 0650 CMSIDL — — CVRCON 0652 — — — CM1CON 0654 CON COE CPOL CM1MSKSRC 0656 — — — CM1MSKCON 0658 HLMS — ...
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TABLE 4-20: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ16GP102 AND dsPIC33FJ16MC102 DEVICES File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — — RPOR3 ...
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TABLE 4-23: PORTA REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name — — — — TRISA 02C0 PORTA 02C2 — — — — LATA 02C4 — — — — ODCA 02C6 — — — — ...
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TABLE 4-27: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> OSCTUN 0748 — — — — Legend ...
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... Register Indirect Post-Modified • Register Indirect Pre-Modified • 5-bit or 10-bit Literal Note: Not all instructions support all of the addressing Individual different subsets of these addressing modes. Preliminary © 2011 Microchip Technology Inc. Table 4-30 form the addressing modes are modes given above. instructions ...
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... Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. © 2011 Microchip Technology Inc. Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the Effective Address (EA). ...
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... MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Preliminary the difference between the Table 4-1). Modulo Addressing is © 2011 Microchip Technology Inc. ...
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... The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. © 2011 Microchip Technology Inc. 4.5.1 BIT-REVERSED ADDRESSING IMPLEMENTATION ...
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... TABLE 4-31: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address DS70652C-page 60 Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word, Bit-Reversed Buffer Bit-Reversed Address Decimal Preliminary A0 Decimal © 2011 Microchip Technology Inc. ...
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... Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. © 2011 Microchip Technology Inc. 4.6.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program ...
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... Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. DS70652C-page 62 Program Counter 0 23 bits 1/0 TBLPAG 8 bits 24 bits Select 1 PSVPAG 0 8 bits 23 bits Preliminary 0 EA 1/0 16 bits bits Byte Select © 2011 Microchip Technology Inc. ...
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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2011 Microchip Technology Inc. • TBLRDH (Table Read High Word mode, this instruction maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom byte’, will always be ‘0’. ...
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... Preliminary 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2011 Microchip Technology Inc. ...
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... Using 1/0 Table Instruction User/Configuration Space Select © 2011 Microchip Technology Inc. ICSP allows a device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of and the alternate programming pin pairs: PGECx/PGEDx), ...
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... NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to “Programming Operations” 26-12: “DC thereby Preliminary (Register 5-1) controls which Section 5.3 for further details. © 2011 Microchip Technology Inc. ...
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... No operation 1100 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = No operation 0000 = No operation Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2011 Microchip Technology Inc. (1) U-0 U-0 — — (1) U-0 R/W-0 — — ...
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... NVMKEY<7:0>: Key Register (write-only) bits DS70652C-page 68 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... Internal Regulator V DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2011 Microchip Technology Inc. A simplified block diagram of the Reset module is shown in Figure Any active source of Reset will make the SYSRST sig- nal active. On system Reset, some of the registers family of associated with the CPU and peripherals are forced to a known Reset state, and some are unaffected ...
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... SWDTEN bit setting. DS70652C-page 70 (1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2011 Microchip Technology Inc. (1) (CONTINUED) Preliminary DS70652C-page 71 ...
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... T T OST LOCK — T LOCK T — OST — — Preliminary in the Oscillator Control Figure 6-2. Total Delay T OSCD OSCD LOCK OSCD OST OSCD OST — OSCD OST LOCK T LOCK OSCD OST T OSCD = 102.4 μs for a OST © 2011 Microchip Technology Inc. ...
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... T BOR extension time BOR T Power-up time 64 ms nominal PWRT delay 900 μs maximum T Fail-safe Clock FSCM Monitor Delay © 2011 Microchip Technology Inc. Vbor V BOR T BOR 3 T PWRT T OSCD Reset Time has elapsed. ensures the voltage regulator output becomes stable. ...
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... BOR PWRT BOR PWRT BOR PWRT Preliminary is too low (V < for proper DD DD BOR crosses the V threshold and the DD BOR ensures the BOR for further + initiated each time V BOR PWRT trip point. BOR V BOR V BOR V BOR © 2011 Microchip Technology Inc. DD ...
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... Watchdog Reset. Refer to Section 23.4 “Watchdog Timer (WDT)” for more information on Watchdog Reset. © 2011 Microchip Technology Inc. 6.7 Trap Conflict Reset If a lower-priority hard trap occurs while a higher-prior- ity trap is being processed, a hard trap conflict Reset occurs. The hard traps include exceptions of priority level 13 through level 15, inclusive ...
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... RESET instruction WDT Time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, BOR POR Preliminary Cleared by: POR, BOR POR, BOR POR, BOR POR POR, BOR PWRSAV instruction, CLRWDT instruction, POR, BOR POR, BOR POR, BOR — — © 2011 Microchip Technology Inc. ...
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... These are summarized in Table 7-1 and Table 7-2. © 2011 Microchip Technology Inc. 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in family ...
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... Table 7-1 for the list of implemented interrupt vectors. DS70652C-page 78 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1) © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Capture 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – ...
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... All Interrupt registers are described in through Register 7-27 Preliminary Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved IPCx INTTREG 7-1. For example, the INT0 (External STATUS/CONTROL REGISTERS Register 7-1 in the following pages. © 2011 Microchip Technology Inc. ...
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... IPL3: CPU Interrupt Priority Level Status bit CPU interrupt priority level is greater than CPU interrupt priority level less Note 1: For complete register details, see 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. © 2011 Microchip Technology Inc. (1) R/C-0 R-0 SB OAB (3) ...
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... Address error trap has not occurred DS70652C-page 82 R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OVBTE COVTE bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. Preliminary DS70652C-page 83 ...
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... Interrupt on positive edge DS70652C-page 84 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — — INT2EP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 INT1EP INT0EP bit Bit is unknown ...
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... T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70652C-page 86 Preliminary © 2011 Microchip Technology Inc. ...
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... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — ...
Page 88
... U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown R/W-0 U-0 PWM1IF — ...
Page 89
... U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 FLTB1IF: PWM1 Fault B Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — ...
Page 90
... Interrupt request not enabled DS70652C-page 90 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 91
... IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. Preliminary DS70652C-page 91 ...
Page 92
... Interrupt request not enabled DS70652C-page 92 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 INT1IE CNIE CMPIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 93
... Interrupt request not enabled bit 13-10 Unimplemented: Read as ‘0’ bit 9 PWM1IE: PWM1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
Page 94
... Interrupt request has not occurred DS70652C-page 94 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 U1EIE FLTB1IE bit Bit is unknown ...
Page 95
... Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 96
... Unimplemented: Read as ‘0’ DS70652C-page 96 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC2IP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 97
... Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 98
... Interrupt source is disabled DS70652C-page 98 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 U1TXIP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 99
... Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 100
... U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 INT1IP<2:0> bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 101
... PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — ...
Page 102
... Unimplemented: Read as ‘0’ DS70652C-page 102 R/W-0 U-0 R/W-1 — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RTCCIP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 103
... Unimplemented: Read as ‘0’ bit 2-0 FLTB1IP<2:0>: PWM1 Fault B Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 R/W-0 — ...
Page 104
... Unimplemented: Read as ‘0’ DS70652C-page 104 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 105
... Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 © 2011 Microchip Technology Inc. U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM< ...
Page 106
... Only user interrupts with a priority level lower can be disabled. Trap sources (level 8-level 15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. Preliminary © 2011 Microchip Technology Inc. ...
Page 107
... F are used interchangeably, except in the case of DOZE mode used with a doze ratio of 1:2 or lower. © 2011 Microchip Technology Inc. The oscillator system for dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/102 devices provides: • External and internal oscillator options as clock sources • An on-chip 4x Phase-Locked Loop (PLL) to scale ...
Page 108
... Instruction execution speed or device operating frequency, F EQUATION 8-1: Preliminary PLL Section 8.1.3 “PLL Configuration”. Section 23.1 “Configuration Configuration bits, FNOSC<2:0> bits, POSCMD<1:0> Table 8-1. is divided OSC ) and the defines the given by: CY DEVICE OPERATING FREQUENCY F OSC = F ------------- CY 2 © 2011 Microchip Technology Inc. ...
Page 109
... Fast RC Oscillator (FRC) with Divide-by-n and PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2011 Microchip Technology Inc. EQUATION 8-2: MS WITH PLL MODE EXAMPLE 1 F OSC ...
Page 110
... PLL modes. DS70652C-page 110 (1) R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) OSC (2) ) OSC Preliminary R/W-y R/W-y (2) NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 111
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2011 Microchip Technology Inc. (1) (CONTINUED) ...
Page 112
... DS70652C-page 112 R/W-1 R/W-0 R/W-0 (2,3) (1,2,3) DOZEN U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2,3) (1,2,3) Preliminary R/W-0 R/W-0 FRCDIV<2:0> bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 113
... Center frequency -12% (6.49 MHz) Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 114
... FRCPLL mode are not permitted. This applies to clock switches in either direc- tion. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. to Section 7. “Oscillator” (DS70186) in the “dsPIC33F/PIC24H Family Reference Manual” for details. © 2011 Microchip Technology Inc. ...
Page 115
... EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2011 Microchip Technology Inc. 9.2 Instruction-Based Power-Saving Modes dsPIC33FJ16GP101/102 and dsPIC33FJ16MC101/ 102 devices have two special power-saving modes that ...
Page 116
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control regis- ters are already configured to enable module operation). Preliminary There are eight possible ® DSC © 2011 Microchip Technology Inc. ...
Page 117
... ADC1 module is enabled Note 1: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode. © 2011 Microchip Technology Inc. R/W-0 R/W-0 U-0 T2MD T1MD — ...
Page 118
... DS70652C-page 118 U-0 U-0 R/W-0 — — IC3MD U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 IC2MD IC1MD bit 8 R/W-0 R/W-0 OC2MD OC1MD bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 119
... Bit is set bit 15-4 Unimplemented: Read as ‘0’ bit 3 CTMUMD: CTMU Module Disable bit 1 = CTMU module is disabled 0 = CTMU module is enabled bit 2-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 R/W-0 — — CMPMD U-0 U-0 U-0 — ...
Page 120
... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 120 Preliminary © 2011 Microchip Technology Inc. ...
Page 121
... WR Port Data Latch Read LAT Read Port © 2011 Microchip Technology Inc. has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through,” in which a port’s digital output can drive the input of a peripheral that shares the same pin. ...
Page 122
... OL each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Preliminary dsPIC33FJ16GP101/102 and © 2011 Microchip Technology Inc. ...
Page 123
... The association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. © 2011 Microchip Technology Inc. 10.4.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it will be mapped to ...
Page 124
... UPDN Output enable default U1TX Output U1RTS Output 4 OC2 Output UPDN Output Preliminary (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> IC1R<4:0> IC2R<4:0> IC3R<4:0> OCFAR<4:0> U1RXR<4:0> U1CTSR<4:0> SS1R<4:0> MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPn RPnR<4:0> Output enable RPn Output Data 19 26 © 2011 Microchip Technology Inc. ...
Page 125
... IOLOCK remains in one state until changed. This allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. © 2011 Microchip Technology Inc. RPn tied to default port pin 00000 RPn tied to Comparator 1 Output 00001 ...
Page 126
... Unimplemented: Read as ‘0’ DS70652C-page 126 R/W-1 R/W-1 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary R/W-1 R/W-1 R/W-1 INT1R<4:0> U-0 U-0 U-0 — — — Bit is unknown © 2011 Microchip Technology Inc. bit 8 bit 0 ...
Page 127
... INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin 11111 = Input tied V 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 128
... Input tied to RP1 00000 = Input tied to RP0 DS70652C-page 128 R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 R/W-1 T2CKR<4:0> Bit is unknown © 2011 Microchip Technology Inc. bit 8 bit 0 ...
Page 129
... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin 11111 = Input tied V 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS ...
Page 130
... Input tied to RP0 DS70652C-page 130 U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 IC3R<4:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 131
... OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin 11111 = Input tied V 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 132
... Input tied to RP1 00000 = Input tied to RP0 DS70652C-page 132 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1RXR<4:0> Bit is unknown © 2011 Microchip Technology Inc. bit 8 bit 0 ...
Page 133
... SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the corresponding RPn pin 11111 = Input tied V 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ...
Page 134
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for © 2011 Microchip Technology Inc. ...
Page 135
... RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP5R<4:0> R/W-0 R/W-0 R/W-0 RP4R< ...
Page 136
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for © 2011 Microchip Technology Inc. ...
Page 137
... RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP13R<4:0> R/W-0 R/W-0 R/W-0 RP12R< ...
Page 138
... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 138 Preliminary © 2011 Microchip Technology Inc. ...
Page 139
... SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2011 Microchip Technology Inc. Timer1 also supports these features: • Timer gate operation • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes family of • Interrupt on 16-bit Period register match or falling ...
Page 140
... DS70652C-page 140 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 (1) TSYNC TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 141
... Timer2 clock and gate inputs are used for the 32-bit timer modules, but an interrupt is generated with the Timer3 interrupt flags. © 2011 Microchip Technology Inc. 12.1 32-bit Operation To configure the Timer2/3 feature timers for 32-bit operation: ...
Page 142
... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70652C-page 142 (1) 1x Gate Sync PR3 PR2 Comparator LSb TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync To CTMU Filter © 2011 Microchip Technology Inc. ...
Page 143
... TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal FIGURE 12-3: TIMER3 (16-BIT) BLOCK DIAGRAM Gate Sync Prescaler F CY TCKPS<1:0> Prescaler Sync (/n) TxCK TCKPS<1:0> To CTMU Filter © 2011 Microchip Technology Inc. Gate Sync TMR2 Comparator PR2 Falling Edge Detect 10 (/ TGATE TCS Preliminary TCKPS<1:0> ...
Page 144
... DS70652C-page 144 U-0 U-0 — — R/W-0 R/W-0 TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 145
... When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (T2CON<3>) register, these bits have no effect. © 2011 Microchip Technology Inc. U-0 U-0 (1) — ...
Page 146
... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 146 Preliminary © 2011 Microchip Technology Inc. ...
Page 147
... ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2011 Microchip Technology Inc. The Input Capture module captures the 16-bit value of the selected Time Base register when an event occurs at the ICx pin. The events that cause a capture event ...
Page 148
... Input capture module turned off DS70652C-page 148 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 149
... OCTSEL TMR3 TMR2 © 2011 Microchip Technology Inc. The Output Compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. family of The state of the output pin changes when the timer value matches the compare register value ...
Page 150
... OCx Rising and Falling edge OCx Falling edge 0 OCx Falling edge OCxR is zero No interrupt 1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero Timer is reset on period match Preliminary (DS70209) for OCxR and — © 2011 Microchip Technology Inc. ...
Page 151
... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 152
... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 152 Preliminary © 2011 Microchip Technology Inc. ...
Page 153
... Fault pins to optionally drive each of the PWM output pins to a defined state • Duty cycle updates configurable to be immediate or synchronized to the PWM time base © 2011 Microchip Technology Inc. 15.1 PWM1: 6-Channel PWM Module This module simplifies the task of generating multiple synchronized PWM outputs ...
Page 154
... Channel 1 Dead-Time Generator 1 Special Event Postscaler SEVTDIR PTDIR Preliminary PWM1H3 Generator and PWM1L3 Override Logic PWM1H2 Generator and Output PWM1L2 Override Logic Driver PWM1H1 Block Generator and PWM1L1 Override Logic FLTA1 FLTB1 Special Event Trigger © 2011 Microchip Technology Inc. (2,3) (3) ...
Page 155
... After the fault pin condition has been cleared, the PWM module restores the PWM output signals on the next PWM period or half-period boundary. © 2011 Microchip Technology Inc. Refer to Section 14. “Motor Control PWM” (DS70187), Reference Manual” for more information on the PWM faults ...
Page 156
... Use builtin function to write 0x0000 to P1FLTBCON register __builtin_write_PWMSFR(&P1FLTBCON, 0x0000, &PWM1KEY); // Enable all PWMs using PWM1CON1 register // Writing to PWM1CON1 register requires unlock sequence // Use builtin function to write 0x0077 to PWM1CON1 register __builtin_write_PWMSFR(&PWM1CON1, 0x0077, &PWM1KEY); DS70652C-page 156 Preliminary © 2011 Microchip Technology Inc. ...
Page 157
... PWM time base operates in a Continuous Up/Down Count mode with interrupts for double PWM updates 10 = PWM time base operates in a Continuous Up/Down Count mode 01 = PWM time base operates in Single Pulse mode 00 = PWM time base operates in a Free-Running mode © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 158
... Bit is cleared R/W-0 R/W-0 R/W-0 PTPER<14:8> R/W-0 R/W-0 R/W-0 PTPER<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 159
... A Special Event Trigger will occur when the PWM time base is counting down Special Event Trigger will occur when the PWM time base is counting up bit 14-0 SEVTCMP<14:0>: Special Event Compare Value bits Note 1: SEVTDIR is compared with PTDIR (P 2: PxSECMP<14:0> is compared with P © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (2) SEVTCMP<14:8> R/W-0 R/W-0 ...
Page 160
... U-0 R/W-0 — — PMOD3 R/W-0 U-0 R/W-0 PEN1H — PEN3L U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Section 15.3 “Write-protected Preliminary R/W-0 R/W-0 PMOD2 PMOD1 bit 8 R/W-0 R/W-0 PEN2L PEN1L bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 161
... Output overrides via the PxOVDCON register occur on next T bit 0 UDIS: PWM Update Disable bit 1 = Updates from Duty Cycle and Period Buffer registers are disabled 0 = Updates from Duty Cycle and Period Buffer registers are enabled © 2011 Microchip Technology Inc. U-0 R/W-0 R/W-0 — ...
Page 162
... DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits DS70652C-page 162 R/W-0 R/W-0 R/W-0 DTB<5:0> R/W-0 R/W-0 R/W-0 DTA<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 163
... Dead time provided from Unit Dead time provided from Unit A bit 0 DTS1I: Dead-Time Select for PWM1 Signal Going Inactive bit 1 = Dead time provided from Unit Dead time provided from Unit A © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — ...
Page 164
... FAOV3L FAOV2H FAOV2L U-0 U-0 R/W-1 — — FAEN3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Section 15.3 “Write-protected Preliminary R/W-0 R/W-0 FAOV1H FAOV1L bit 8 R/W-1 R/W-1 FAEN2 FAEN1 bit Bit is unknown Section 15.2 © 2011 Microchip Technology Inc. ...
Page 165
... The PxFLTACON register is a write-protected register. Refer to Registers” for more information on the unlock sequence. 5: During any reset event, FLTB1 is enabled by default and must be cleared as described in “PWM Faults”. © 2011 Microchip Technology Inc. (1,2,3,4,5) R/W-0 R/W-0 R/W-0 FBOV3L FBOV2H FBOV2L ...
Page 166
... DS70652C-page 166 R/W-1 R/W-1 R/W-1 POVD3L POVD2H POVD2L R/W-0 R/W-0 R/W-0 POUT3L POUT2H POUT2L U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 POVD1H POVD1L bit 8 R/W-0 R/W-0 POUT1H POUT1L bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 167
... R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC3<15:0>: PWM Duty Cycle 3 Value bits © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PDC1<15:8> R/W-0 R/W-0 R/W-0 PDC1<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 168
... Family Reference Manual” for details on the unlock sequence. DS70652C-page 168 R/W-0 R/W-0 R/W-0 PWMKEY<15:8> R/W-0 R/W-0 R/W-0 PWMKEY<7:0> Unimplemented, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 169
... SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF © 2011 Microchip Technology Inc. The Serial Peripheral Interface (SPI) module is a syn- chronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices can be serial EEPROMs, shift regis- ters, display drivers, analog-to-digital converters, etc. ...
Page 170
... DS70652C-page 170 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...
Page 171
... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 DISSCK DISSDO ...
Page 172
... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. DS70652C-page 172 (3) (3) Preliminary © 2011 Microchip Technology Inc. ...
Page 173
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application. © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 174
... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 174 Preliminary © 2011 Microchip Technology Inc. ...
Page 175
... I C supports multi-master operation, detects bus collision and arbitrates accordingly © 2011 Microchip Technology Inc. 17.1 Operating Modes The hardware fully implements all the master and slave functions of the I specifications, as well as 7-bit and 10-bit addressing. ...
Page 176
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2011 Microchip Technology Inc. ...
Page 177
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2011 Microchip Technology Inc. R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
Page 178
... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence 0 = Start condition not in progress DS70652C-page 178 2 C master, applicable during master receive) C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte 2 C master master) Preliminary 2 C master) © 2011 Microchip Technology Inc. ...
Page 179
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2011 Microchip Technology Inc. U-0 U-0 — — R/C-0 HSC ...
Page 180
... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70652C-page 180 2 C slave device address byte. Preliminary © 2011 Microchip Technology Inc. ...
Page 181
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 182
... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 182 Preliminary © 2011 Microchip Technology Inc. ...
Page 183
... Baud Rate Generator Hardware Flow Control UART Receiver UART Transmitter © 2011 Microchip Technology Inc. The primary features of the UART module are: • Full-Duplex, 8-bit or 9-bit Data Transmission through the UxTX and UxRX pins • Even, Odd Parity Options (for 8-bit data) • ...
Page 184
... DS70652C-page 184 MODE REGISTER x R/W-0 R/W-0 U-0 (2) IREN RTSMD R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-0 R/W-0 — UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 185
... Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2011 Microchip Technology Inc. MODE REGISTER (CONTINUED) x Preliminary DS70652C-page 185 ...
Page 186
... U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R-0 R-1 (1) UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Clearable bit x = Bit is unknown © 2011 Microchip Technology Inc. ...
Page 187
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. © 2011 Microchip Technology Inc. STATUS AND CONTROL REGISTER (CONTINUED) x Preliminary DS70652C-page 187 ...
Page 188
... AND dsPIC33FJ16MC101/102 NOTES: DS70652C-page 188 Preliminary © 2011 Microchip Technology Inc. ...
Page 189
... Depending on the particular device pinout, the ADC can have up to six analog input pins, designated AN0 through AN5. Block diagrams of the ADC module are shown in Figure 19-1 and Figure 19-2. © 2011 Microchip Technology Inc. 19.2 ADC Initialization To configure the ADC module: 1. Select port (ADxPCFGH<15:0> or ADxPCFGL<15:0>). ...
Page 190
... CH123NA CH123NB Alternate Input Selection Note 1: Internally connected to CTMU module. 2: This selection is only used with CTMU capacitive and time measurement. DS70652C-page 190 (1) CTMUI Preliminary ADC1BUF0 ADC1BUF1 ADC1BUF2 V V REFH REFL SAR ADC ADC1BUFE ADC1BUFF © 2011 Microchip Technology Inc. ...
Page 191
... CH123SB CH2 AVss CH123NA CH123NB AN2 AN5 CH123SA CH123SB CH3 AVss CH123NA CH123NB Alternate Input Selection Note 1: Internally connected to CTMU module. 2: This selection is only used with CTMU capacitive and time measurement. © 2011 Microchip Technology Inc. (1) CTMUI Preliminary AV AV ...
Page 192
... ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADC Internal (1) RC Clock T CY OSC ( Note 1: See the ADC specifications in DS70652C-page 192 ADxCON3<5:0> 6 ADC Conversion Clock Multiplier 5,..., 64 Section 26.0 “Electrical Characteristics” Preliminary ADxCON3<15> for the exact RC clock value. © 2011 Microchip Technology Inc. ...
Page 193
... If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1. If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC ≠ 000, automatically cleared by hardware to end sampling and start conversion. Note 1: Available only on dsPIC33FJ16MC101/102 devices. © 2011 Microchip Technology Inc. U-0 U-0 — — ...
Page 194
... Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion. Note 1: Available only on dsPIC33FJ16MC101/102 devices. DS70652C-page 194 Preliminary © 2011 Microchip Technology Inc. ...
Page 195
... Always starts filling buffer from the beginning bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A © 2011 Microchip Technology Inc. U-0 U-0 R/W-0 — ...
Page 196
... This bit only used if AD1CON1<7:5> (SSRC<2:0> This bit is not used if AD1CON3<15> (ADRC DS70652C-page 196 R/W-0 R/W-0 R/W-0 SAMC<4:0> R/W-0 R/W-0 R/W-0 (2) ADCS<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ( Preliminary R/W-0 R/W-0 (1) bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 197
... CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 dsPIC33FJ16GP102 and dsPIC33FJ16MC102 devices only CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 © 2011 Microchip Technology Inc. U-0 U-0 R/W-0 — ...
Page 198
... All other values than those listed are Reserved. DS70652C-page 198 R/W-0 R/W-0 R/W-0 CH0SB<4:0> R/W-0 R/W-0 R/W-0 CH0SA<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary R/W-0 R/W-0 (1) bit 8 R/W-0 R/W-0 (1) bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 199
... On devices without 6 analog inputs, all AD1CSSL bits can be selected by user application. However, inputs selected for scan without a corresponding input on device converts V 2: CSSx = ANx, where through 5. 3: CTMU temperature sensor input cannot be scanned. © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — ...
Page 200
... U-0 — — R/W-0 R/W-0 (4) (4) (4) PCFG4 PCFG3 PCFG2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (4) Preliminary (1,2,3) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 R/W-0 (4) (4) (4) PCFG1 PCFG0 bit Bit is unknown SS © 2011 Microchip Technology Inc. ...