DSPIC33FJ16MC304-E/PT Microchip Technology, DSPIC33FJ16MC304-E/PT Datasheet - Page 187

16-bit DSC, 16KB Flash,Motor,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY

DSPIC33FJ16MC304-E/PT

Manufacturer Part Number
DSPIC33FJ16MC304-E/PT
Description
16-bit DSC, 16KB Flash,Motor,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC304-E/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ16MC304-E/PTTR
DSPIC33FJ16MC304-E/PTTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ16MC304-E/PT
Manufacturer:
Microchip
Quantity:
175
Part Number:
DSPIC33FJ16MC304-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
REGISTER 18-1:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
I2CEN
GCEN
R/W-0
R/W-0
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module. All I
Unimplemented: Read as ‘0’
I2CSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters an Idle mode
0 = Continue module operation in Idle mode
SCLREL: SCLx Release Control bit (when operating as I
1 = Release SCLx clock
0 = Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear
at beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1 = IPMI mode is enabled; all addresses Acknowledged
0 = IPMI mode disabled
A10M: 10-bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control disabled
0 = Slew rate control enabled
SMEN: SMbus Input Levels bit
1 = Enable I/O pin thresholds compliant with SMbus specification
0 = Disable SMbus input thresholds
GCEN: General Call Enable bit (when operating as I
1 = Enable interrupt when a general call address is received in the I2CxRSR
0 = General call address disabled
STREN: SCLx Clock Stretch Enable bit (when operating as I
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
STREN
R/W-0
(module is enabled for reception)
U-0
I2CxCON: I2Cx CONTROL REGISTER
U = Unimplemented bit, read as ‘0’
W = Writable bit
‘1’ = Bit is set
I2CSIDL
ACKDT
R/W-0
R/W-0
R/W-1 HC
R/W-0 HC
SCLREL
ACKEN
2
C pins are controlled by port functions
HS = Set in hardware
‘0’ = Bit is cleared
R/W-0 HC
IPMIEN
R/W-0
RCEN
2
C slave)
2
C slave)
R/W-0 HC
2
R/W-0
A10M
C slave)
PEN
HC = Cleared in hardware
x = Bit is unknown
R/W-0 HC
DISSLW
R/W-0
RSEN
DS70283H-page 187
R/W-0 HC
R/W-0
SMEN
SEN
bit 8
bit 0

Related parts for DSPIC33FJ16MC304-E/PT