DSPIC33FJ16MC304-E/PT Microchip Technology, DSPIC33FJ16MC304-E/PT Datasheet - Page 66

• Manufacturer Part Number: DSPIC33FJ16MC304-E/PT
• Description: 16-bit DSC, 16KB Flash,Motor,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC304-E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC33FJ16MC304-E/PTTR; DSPIC33FJ16MC304-E/PTTR

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
6.1
The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
family of devices have two types of Reset:
• Cold Reset
• Warm Reset
A cold Reset is the result of a Power-on Reset (POR)
or a Brown-out Reset (BOR). On a cold Reset, the
FNOSC configuration bits in the FOSC device
configuration register selects the device clock source.
A warm Reset is the result of all other reset sources,
including the RESET instruction. On warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
bits (COSC<2:0>) in the Oscillator Control register
(OSCCON<14:12>).
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is detailed below and is shown in
Figure
1.
TABLE 6-1:
DS70283H-page 66
FRC, FRCDIV16,
FRCDIVN
FRCPLL
XT
HS
EC
XTPLL
HSPLL
ECPLL
SOSC
LPRC
Note 1:
Oscillator Mode
POR: A POR circuit holds the device in Reset
when the power supply is turned on. The POR
circuit is active until V
threshold and the delay T
6-2.
2:
3:
System Reset
T
times vary with crystal characteristics, load capacitance, etc.
T
10 MHz crystal and T
T
OSCD
OST
LOCK
= Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, T
OSCILLATOR DELAY
= PLL lock time (1.5 ms nominal), if PLL is enabled.
= Oscillator Start-up Delay (1.1 μs max for FRC, 70 μs max for LPRC). Crystal Oscillator start-up
Start-up Delay
Oscillator
DD
POR
T
T
T
T
T
T
T
T
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
—
—
OST
crosses the V
has elapsed.
= 32 ms for a 32 kHz crystal.
Oscillator Start-up
POR
Timer
T
T
T
T
T
OST
OST
OST
OST
OST
—
—
—
—
—
2.
3.
4.
5.
6.
BOR: The on-chip voltage regulator has a BOR
circuit that keeps the device in Reset until V
crosses the V
has elapsed. The delay T
voltage regulator output becomes stable.
PWRT Timer: The programmable power-up
timer continues to hold the processor in Reset
for a specific period of time (T
BOR. The delay T
power
appropriate level for full-speed operation. After
the delay T
becomes inactive, which in turn enables the
selected oscillator to start generating clock
cycles.
Oscillator Delay: The total delay for the clock to
be ready for various clock source selections is
given in
“Oscillator
information.
When the oscillator clock is ready, the processor
begins execution from location 0x000000. The
user application programs a GOTO instruction at
the reset address, which redirects program
execution to the appropriate start-up routine.
The Fail-Safe Clock Monitor (FSCM), if enabled,
begins to monitor the system clock when the
system clock is ready and the delay T
elapsed.
PLL Lock Time
supplies
T
T
T
T
Table
LOCK
LOCK
LOCK
LOCK
—
—
—
—
—
—
PWRT
BOR
Configuration”
6-1. Refer to
PWRT
threshold and the delay T
has elapsed, the SYSRST
© 2011 Microchip Technology Inc.
have
ensures that the system
BOR
T
T
OSCD
OSCD
OST
stabilized
T
T
T
T
ensures that the
OSCD
Total Delay
= 102.4 μs for a
OSCD
OSCD
OSCD
PWRT
+ T
+ T
T
T
T
for
OSCD
OSCD
Section 8.0
LOCK
OST
OST
—
+ T
+ T
+ T
+ T
) after a
at
LOCK
+ T
+ T
OST
OST
OST
more
FSCM
BOR
LOCK
LOCK
the
DD