DSPIC33FJ16MC304-E/PT Microchip Technology, DSPIC33FJ16MC304-E/PT Datasheet - Page 70

• Manufacturer Part Number: DSPIC33FJ16MC304-E/PT
• Description: 16-bit DSC, 16KB Flash,Motor,40 MIPS,nanoWatt 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC304-E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC33FJ16MC304-E/PTTR; DSPIC33FJ16MC304-E/PTTR

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
6.7
To maintain the integrity of the peripheral pin select
control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occur (such as cell
disturbances caused by ESD or other external events),
a configuration mismatch Reset occurs.
The Configuration Mismatch Flag bit (CM) in the
Reset Control register (RCON<9>) is set to indicate
the
Section 10.0 “I/O Ports”
configuration mismatch Reset.
6.8
An illegal condition device Reset occurs due to the
following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
The Illegal Opcode or Uninitialized W Access Reset
Flag bit (IOPUWR) in the Reset Control register
(RCON<14>) is set to indicate the illegal condition
device Reset.
6.8.1
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
The illegal opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the illegal opcode Reset, use only the lower 16 bits of
TABLE 6-3:
DS70283H-page 70
TRAPR (RCON<15>)
IOPWR (RCON<14>)
CM (RCON<9>)
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
Note: All Reset flag bits can be set or cleared by user software.
Note:
configuration
Configuration Mismatch Reset
Illegal Condition Device Reset
The configuration mismatch feature and
associated reset flag is not available on all
devices.
ILLEGAL OPCODE RESET
Flag Bit
RESET FLAG BIT OPERATION
mismatch
for more information on the
Reset.
Trap conflict event
Illegal opcode or uninitialized
W register access or Security Reset
Configuration Mismatch
MCLR Reset
RESET instruction
WDT time-out
PWRSAV #SLEEP instruction
PWRSAV #IDLE instruction
POR, BOR
POR
Refer
to
Set by:
each program memory section to store the data values.
The upper 8 bits should be programmed with 3Fh,
which is an illegal opcode value.
6.8.2
Any attempts to use the uninitialized W register as an
address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
resets and is considered uninitialized until written to.
6.8.3
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a security Reset.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
branch instruction.
The VFC occurs when the Program Counter is
reloaded with an Interrupt or Trap vector.
Refer to
CodeGuard™ Security”
Security Reset.
6.9
The user application can read the Reset Control regis-
ter (RCON) after any device Reset to determine the
cause of the reset.
Table 6-3
operation.
Note:
Using the RCON Status Bits
provides a summary of the reset flag bit
UNINITIALIZED W REGISTER
RESET
SECURITY RESET
Section 21.8 “Code Protection and
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
POR,BOR
POR,BOR
POR,BOR
POR
POR,BOR
PWRSAV instruction,
CLRWDT instruction, POR,BOR
POR,BOR
POR,BOR
© 2011 Microchip Technology Inc.
for more information on
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