DSPIC33FJ16MC304T-I/ML Microchip Technology, DSPIC33FJ16MC304T-I/ML Datasheet
DSPIC33FJ16MC304T-I/ML
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DSPIC33FJ16MC304T-I/ML Summary of contents
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... Microchip Technology Inc. dsPIC33FJ16MC304 High-Performance, 16-bit Digital Signal Controllers Data Sheet DS70283H ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Capture on up, down or both edges - 16-bit capture input functions - 4-deep FIFO on each capture • Output Compare (up to two channels): - Single or Dual 16-Bit Compare mode - 16-bit Glitchless PWM mode © 2011 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Interrupt Controller: • 5-cycle latency • available interrupt sources • ...
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... LIN bus support ® - IrDA encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS Packaging: • 28-pin SDIP/SOIC/QFN-S • 44-pin QFN/TQFP Note: See Table 1 for the exact peripheral features per device. © 2011 Microchip Technology Inc. ...
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... CONTROLLER FAMILIES Device Pins dsPIC33FJ32MC202 dsPIC33FJ32MC204 dsPIC33FJ16MC304 Note 1: Only two out of three timers are remappable. 2: Only PWM fault inputs are remappable. 3: Only two out of three interrupts are remappable. © 2011 Microchip Technology Inc. Remappable Peripherals (1) ( 6ch 1 (2) 2ch (1) ( 6ch 1 (2) 2ch (1) ...
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... PWM1L2/RP13 1 21 PWM1H2/RP12 2 20 PGEC2/EMUC2/TMS/PWM1L3/RP11 3 19 dsPIC33FJ32MC202 PGED2/EMUD2/TDI/PWM1H3/RP10 CAP TDO/PWM2L1/SDA1/RP9 externally. = Pins are tolerant (1) /CN11/RB15 (1) /CN12/RB14 (1) /CN13/RB13 (1) /CN14/RB12 (1) /CN15/RB11 (1) /CN16/RB10 (1) /CN21/RB9 (1) /CN22/RB8 (1) /CN24/RB6 = Pins are tolerant (1) /CN13/RB13 (1) /CN14/RB12 (1) /CN15/RB11 (1) /CN16/RB10 (1) /CN21/RB9 Table 1 for the list of available © 2011 Microchip Technology Inc. ...
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... OSC1/CLKI/CN30/RA2 30 OSC2/CLKO/CN29/RA3 31 TDO/RA8 32 (1) SOSCI/RP4 /CN1/RB4 33 34 Note 1: The RPn pins can be used by any remappable peripheral. See peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected © 2011 Microchip Technology Inc PWM1L2/RP13 11 PWM1H2/RP12 10 PGEC2/EMUC2/PWM1L3/RP11 ...
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... Note 1: The RPn pins can be used by any remappable peripheral. See peripherals. DS70283H-page 8 11 PWM1L2/RP13 10 PWM1H2/RP12 9 PGEC2/EMUC2/PWM1L3/RP11 8 PGED2/EMUD2/PWM1H3/RP10 7 V CAP dsPIC33FJ32MC204 dsPIC33FJ16MC304 (1) 5 RP25 /CN19/RC9 (1) 4 RP24 /CN20/RC8 3 PWM2L1/RP23 2 PWM2H1/RP22 1 SDA1/RP9 = Pins are tolerant (1) /CN13/RB13 (1) /CN14/RB12 (1) /CN15/RB11 (1) /CN16/RB10 (1) /CN17/RC7 (1) /CN18/RC6 (1) /CN21/RB9 Table 1 for the list of available © 2011 Microchip Technology Inc. ...
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... High Temperature Electrical Characteristics ............................................................................................................................ 279 26.0 Packaging Information.............................................................................................................................................................. 289 Appendix A: Revision History............................................................................................................................................................. 303 Index ................................................................................................................................................................................................. 313 The Microchip Web Site ..................................................................................................................................................................... 317 Customer Change Notification Service .............................................................................................................................................. 317 Customer Support .............................................................................................................................................................................. 317 Reader Response .............................................................................................................................................................................. 318 Product Identification System ............................................................................................................................................................ 319 © 2011 Microchip Technology Inc. DS70283H-page 9 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS70283H-page 10 to receive the most current information on all of our products © 2011 Microchip Technology Inc. ...
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... Figure 1-1 shows a general block diagram of the core and peripheral modules dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2011 Microchip Technology Inc. Reference in in the DS70283H-page 11 ...
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... EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support MCLR OC/ SPI1 ADC1 PWM1-2 QEI CNx I2C1 PORTA PORTB 16 PORTC Remappable Pins 16-bit ALU 16 PWM 2 Ch PWM 6 Ch “Pin Diagrams” for the specific pins © 2011 Microchip Technology Inc. ...
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... No Legend: CMOS = CMOS compatible input or output Schmitt Trigger input with CMOS levels; PPS = Peripheral Pin Select © 2011 Microchip Technology Inc. Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
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... Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Analog = Analog input Output Power I = Input © 2011 Microchip Technology Inc. ...
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... ADC module is implemented Note: The AV and connected independent of the ADC voltage reference source. © 2011 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • ...
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... Ensure that the MCLR pin V and V specifications are met MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Elec- trostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V and V specifications are met © 2011 Microchip Technology Inc. is ...
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... REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 ® • “Using MPLAB REAL ICE™ In-Circuit Emulator” (poster) DS51749 © 2011 Microchip Technology Inc. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “ ...
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... Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect 10k resistor between V and the unused pins. DS70283H-page 18 SS © 2011 Microchip Technology Inc. ...
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... Figure 3-2. © 2011 Microchip Technology Inc. 3.1 Data Addressing Overview The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred and Y data memory. Each memory block has its own independent Address Generation Unit (AGU) ...
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... Data Latch Data Latch PCL X RAM Y RAM Address Address Loop Latch Control Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 24 Instruction Reg DSP Engine Register Array Divide Support 16-bit ALU 16 To Peripheral Modules © 2011 Microchip Technology Inc. ...
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... Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG OAB SAB DA SRH © 2011 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 PC0 0 Program Space Visibility Page Address ...
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... IPL<3> The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). DS70283H-page 22 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2011 Microchip Technology Inc. ...
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... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). © 2011 Microchip Technology Inc. (2) DS70283H-page 23 ...
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... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70283H-page 24 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2011 Microchip Technology Inc. ...
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... The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. © 2011 Microchip Technology Inc. 3.6 DSP Engine The DSP engine consists of a high-speed 17-bit x ...
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... FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70283H-page 26 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2011 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. © 2011 Microchip Technology Inc. 3.6.2.1 The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input. • ...
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... MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. subject to data saturation (see Saturation”). For © 2011 Microchip Technology Inc. ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2011 Microchip Technology Inc. 3.6.4 BARREL SHIFTER The barrel shifter can perform up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70283H-page 30 © 2011 Microchip Technology Inc. ...
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... Device Configuration 0xF80000 Registers 0xF80017 0xF80018 Reserved 0xFEFFFE 0xFF0000 DEVID (2) 0xFFFFFE © 2011 Microchip Technology Inc. 4.1 Program Address Space The program address dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 and devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program ...
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... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector least significant word Instruction Width Table”. PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2011 Microchip Technology Inc. ...
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... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2011 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...
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... Optionally Mapped into Program Memory 0xFFFF DS70283H-page 34 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0BFE 0x0C00 Y Data RAM (Y) 0x0FFE 0x1000 0x1FFE 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE 8 Kbyte Near Data Space © 2011 Microchip Technology Inc. ...
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... X and Y address space also the X data prefetch path for the dual operand DSP instructions (MAC class). © 2011 Microchip Technology Inc. The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED) SFR SFR Name Bit 15 Bit 14 Bit 13 Addr XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — Legend unknown value on Reset, — ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — ...
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TABLE 4-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 4-8: 6-OUTPUT PWM1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P1TCON 01C0 PTEN — PTSIDL — P1TMR 01C2 PTDIR P1TPER 01C4 — P1SECMP 01C6 SEVTDIR PWM1CON1 01C8 — — — — PWM1CON2 01CA ...
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TABLE 4-10: QEI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name — QEI1CON 01E0 CNTERR QEISIDL INDEX DFLT1CON 01E2 — — — — POS1CNT 01E4 MAX1CNT 01E6 Legend uninitialized bit, — = unimplemented, ...
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TABLE 4-14: ADC1 REGISTER MAP FOR dsPIC33FJ32MC202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
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TABLE 4-15: ADC1 REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0300 ADC1BUF0 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ...
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TABLE 4-16: PERIPHERAL PIN SELECT INPUT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — — RPINR1 0682 — — — — RPINR3 0686 — — — RPINR7 068E — — — ...
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TABLE 4-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32MC204 AND dsPIC33FJ16MC304 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — — RPOR3 06C6 ...
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TABLE 4-21: PORTB REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 PORTB 02CA RB15 RB14 RB13 RB12 LATB 02CC LATB15 LATB14 LATB13 LATB12 ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 ...
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TABLE 4-24: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0760 WR WREN WRERR — NVMKEY 0766 — — — — Legend unknown value on Reset, — = unimplemented, read as ...
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... Register Indirect Pre-Modified • 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individ- ual instructions can support different subsets of these addressing modes. © 2011 Microchip Technology Inc. Table 4-26 form the addressing modes are ...
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... Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. © 2011 Microchip Technology Inc. Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the Effective Address (EA). ...
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... MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Modulo Addressing EA the difference between the Table 4-1). Modulo Addressing is © 2011 Microchip Technology Inc. ...
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... Addressing) • The BREN bit is set in the XBREV register • The addressing mode used is Register Indirect with Pre-Increment or Post-Increment © 2011 Microchip Technology Inc. If the length of a bit-reversed buffer the last ‘N’ bits of the data buffer start address must be zeros. ...
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... TABLE 4-27: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address DS70283H-page 52 Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address Decimal Decimal © 2011 Microchip Technology Inc. ...
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... Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. © 2011 Microchip Technology Inc. 4.6.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program ...
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... Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS70283H-page 54 Program Counter 0 23 bits 1/0 TBLPAG 8 bits 24 bits Select 1 0 PSVPAG 8 bits 23 bits 0 EA 1/0 16 bits bits Byte Select © 2011 Microchip Technology Inc. ...
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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2011 Microchip Technology Inc Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘ ...
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... PSV Area 0x800000 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2011 Microchip Technology Inc. ...
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... Table Instruction User/Configuration Space Select © 2011 Microchip Technology Inc. customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be pro- grammed ...
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... Equation 5-2. MINIMUM ROW WRITE TIME 11064 Cycles = × × 0.05 1 0.00375 – Equation 5-3. MAXIMUM ROW WRITE TIME 11064 Cycles = × × – – 1 0.05 1 0.00375 (Register 5-1) controls which Section 5.3 for further details. © 2011 Microchip Technology Inc. ...
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... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be Reset on a POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2011 Microchip Technology Inc. (1) U-0 U-0 — — (1) U-0 R/W-0 — ...
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... NVMKEY<7:0>: Key Register (write-only) bits DS70283H-page 60 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2011 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted © 2011 Microchip Technology Inc. ...
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... V DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2011 Microchip Technology Inc. A simplified block diagram of the Reset module is shown in Figure Any active source of reset will make the SYSRST signal active. On system Reset, some of the registers associated with the CPU and peripherals are forced to a known Reset state and some are unaffected ...
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... SWDTEN bit setting. DS70283H-page 64 (1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) U-0 R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2011 Microchip Technology Inc. (1) (CONTINUED) DS70283H-page 65 ...
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... SYSRST 6-1. Refer to Section 8.0 for more FSCM Total Delay T OSCD OSCD LOCK OSCD OST OSCD OST — OSCD OST LOCK OSCD OST LOCK T LOCK OSCD OST T OSCD = 102.4 μs for a OST © 2011 Microchip Technology Inc. ...
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... GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay T © 2011 Microchip Technology Inc. Vbor V BOR ...
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... The BOR crosses DD has elapsed. The BOR ensures the voltage regulator output ) is programmed by PWRT Reset Timer Value Select Section 21.0 “Special Features” initiated each time V BOR PWRT trip point BOR © 2011 Microchip Technology Inc. bits DD ...
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... Reset state. This Reset state will not re-initialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST is released at the next instruction cycle, and the reset vector fetch will commence. © 2011 Microchip Technology Inc BOR PWRT ...
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... The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. Cleared by: POR,BOR POR,BOR POR,BOR POR POR,BOR PWRSAV instruction, CLRWDT instruction, POR,BOR POR,BOR POR,BOR — — © 2011 Microchip Technology Inc. ...
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... These are summarized in Table 7-1 and Table 7-2. © 2011 Microchip Technology Inc. 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in AIVT is provided (INTCON2< ...
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... Table 7-1 for the list of implemented interrupt vectors. DS70283H-page 72 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 (1) (1) © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Capture 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – Input Capture 2 0x000120 OC2 – ...
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... FLTA1 – PWM1 Fault A Reserved U1E – UART1 Error Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWM2 – PWM2 Period Match FLTA2 – PWM2 Fault A Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved © 2011 Microchip Technology Inc. ...
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... IECx The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2011 Microchip Technology Inc. 7.3.4 IPCx The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...
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... U = Unimplemented bit, read as ‘0’ (2) Register 3-2: “CORCON: CORE Control R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 Register”. R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set Register”. © 2011 Microchip Technology Inc. ...
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... MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...
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... STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70283H-page 78 © 2011 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 ...
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... Interrupt request has not occurred DS70283H-page 80 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. DS70283H-page 81 ...
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... Interrupt request has not occurred DS70283H-page 82 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 PWM1IF: PWM1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 R/W-0 — — QEIIF U-0 ...
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... Unimplemented: Read as ‘0’ DS70283H-page 84 U-0 U-0 R/W-0 — — FLTA2IF U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. R/W-0 U-0 PWM2IF — bit 8 R/W-0 U-0 U1EIF — bit Bit is unknown ...
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... T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — ...
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... REGISTER 7-9: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70283H-page 86 © 2011 Microchip Technology Inc. ...
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... MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...
Page 88
... Unimplemented: Read as ‘0’ DS70283H-page 88 U-0 U-0 R/W-0 — — QEIIE U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. R/W-0 U-0 PWM1IE — bit 8 U-0 U-0 — — bit Bit is unknown ...
Page 89
... Interrupt request not enabled bit 8-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 R/W-0 — — FLA2IE U-0 U-0 U-0 — ...
Page 90
... Interrupt is priority 1 000 = Interrupt source is disabled DS70283H-page 90 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 91
... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — ...
Page 92
... Interrupt is priority 1 000 = Interrupt source is disabled DS70283H-page 92 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 93
... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — ...
Page 94
... Interrupt is priority 1 000 = Interrupt source is disabled DS70283H-page 94 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 95
... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — ...
Page 96
... Unimplemented: Read as ‘0’ DS70283H-page 96 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 97
... PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — ...
Page 98
... U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 99
... PWM2IP<2:0>: PWM2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 R/W-0 — — R/W-0 U-0 U-0 — ...
Page 100
... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70283H-page 100 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 101
... ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2011 Microchip Technology Inc. 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
Page 102
... NOTES: DS70283H-page 102 © 2011 Microchip Technology Inc. ...
Page 103
... F P Throughout this document, be different when DOZE mode is used with any ratio other than 1:1 which is the default. © 2011 Microchip Technology Inc. The oscillator system for dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices provides: • External and internal oscillator options as clock sources. ...
Page 104
... SYSTEM CLOCK SELECTION Section 21.1 “Configuration Configuration bits, FNOSC<2:0> bits, POSCMD<1:0> Table 8-1. is divided OSC ) and the defines the given by: CY DEVICE OPERATING FREQUENCY F OSC F = ------------- CY 2 PLL CONFIGURATION Figure 8-2. factor ‘N1’ is selected using © 2011 Microchip Technology Inc. the ...
Page 105
... Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2011 Microchip Technology Inc. ’, • If PLLDIV<8:0> = 0x1E, then 32. This yields a VCO output 160 MHz, which is within the 100-200 MHz ranged needed. • ...
Page 106
... This register is reset only on a Power-on Reset (POR). DS70283H-page 106 (1,3) R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) © 2011 Microchip Technology Inc. R/W-y R/W-y (2) NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...
Page 107
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (1,3) (CONTINUED) DS70283H-page 107 ...
Page 108
... This register is reset only on a Power-on Reset (POR). DS70283H-page 108 (2) R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 109
... Note 1: This register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (1) U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ...
Page 110
... This register is reset only on a Power-on Reset (POR). DS70283H-page 110 (2) U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) TUN<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 111
... NOSC control bits. If they are the same, the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. © 2011 Microchip Technology Inc valid clock switch has been initiated, the LOCK (OSCCON<3>) status bits are cleared. ...
Page 112
... NOTES: DS70283H-page 112 © 2011 Microchip Technology Inc. ...
Page 113
... EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2011 Microchip Technology Inc. 9.2 Instruction-Based Power-Saving Modes dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices have two special power-saving modes that are ...
Page 114
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). There are eight possible ® DSC © 2011 Microchip Technology Inc. ...
Page 115
... AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled Note 1: PCFGx bits have no effect if the ADC module is disabled by setting this bit. In this case, all port pins multiplexed with ANx will be in Digital mode. © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T2MD T1MD ...
Page 116
... Output Compare 1 module is enabled DS70283H-page 116 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC2MD IC1MD bit 8 R/W-0 R/W-0 OC2MD OC1MD bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 117
... Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4 PWM2MD: PWM2 Module Disable bit 1 = PWM2 module is disabled 0 = PWM2 module is enabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 U-0 ...
Page 118
... NOTES: DS70283H-page 118 © 2011 Microchip Technology Inc. ...
Page 119
... WR Port Data Latch Read LAT Read Port © 2011 Microchip Technology Inc. the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the same pin. how ports are shared with other peripherals and the associated I/O pin to which they are connected ...
Page 120
... CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Examples are shown in NOP. Example 10-2. This also applies to dsPIC33FJ32MC202/204 and © 2011 Microchip Technology Inc. ...
Page 121
... The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on whether an input or output is being mapped. © 2011 Microchip Technology Inc. 10.6.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it will be mapped to ...
Page 122
... RPINR14 QEB RPINR14 INDX RPINR15 U1RX RPINR18 U1CTS RPINR18 SDI1 RPINR20 SCK1 RPINR20 SS1 RPINR21 (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> FLTA1R<4:0> FLTA2R<4:0> QEA1R<4:0> QEB1R<4:0> INDX1R<4:0> U1RXR<4:0> U1CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> © 2011 Microchip Technology Inc. ...
Page 123
... RPnR<4:0> NULL U1TX U1RTS SDO1 SCK1OUT SS1OUT OC1 OC2 UPDN © 2011 Microchip Technology Inc. FIGURE 10-3: U1TX Output Enable 10-26). The U1RTS Output Enable 4 OC2 Output Enable UPDN Output Enable U1TX Output U1RTS Output 4 UPDN Output RPn tied to default port pin ...
Page 124
... Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. built-in C © 2011 Microchip Technology Inc. ...
Page 125
... Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. and R/W-1 R/W-1 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 126
... Input tied to RP1 00000 = Input tied to RP0 DS70283H-page 126 U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 INT2R<4:0> Bit is unknown © 2011 Microchip Technology Inc. bit 8 bit 0 ...
Page 127
... T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS ...
Page 128
... Input tied to RP1 00000 = Input tied to RP0 DS70283H-page 128 R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 IC2R<4:0> bit 8 R/W-1 R/W-1 R/W-1 IC1R<4:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 129
... IC7R<4:0>: Assign Input Capture 7 (IC7) to the corresponding pin RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS ...
Page 130
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 OCFAR<4:0> Bit is unknown U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 FLTA1R<4:0> Bit is unknown © 2011 Microchip Technology Inc. bit 8 bit 0 bit 8 bit 0 ...
Page 131
... FLTA2R<4:0>: Assign PWM2 Fault (FLTA2) to the corresponding RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 FLTA2R<4:0> Unimplemented bit, read as ‘0’ ...
Page 132
... Input tied to RP1 00000 = Input tied to RP0 DS70283H-page 132 R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 QEB1R<4:0> R/W-1 R/W-1 R/W-1 QEA1R<4:0> Bit is unknown © 2011 Microchip Technology Inc. bit 8 bit 0 ...
Page 133
... INDX1R<4:0>: Assign QEI INDEX (INDX) to the corresponding RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 INDX1R<4:0> Unimplemented bit, read as ‘0’ ...
Page 134
... Input tied to RP1 00000 = Input tied to RP0 DS70283H-page 134 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1RXR<4:0> Bit is unknown © 2011 Microchip Technology Inc. bit 8 bit 0 ...
Page 135
... SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin bits 11111 = Input tied V 11001 = Input tied to RP25 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS ...
Page 136
... Input tied to RP1 00000 = Input tied to RP0 DS70283H-page 136 U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 SS1R<4:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 137
... RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 R/W-0 R/W-0 RP0R< ...
Page 138
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for © 2011 Microchip Technology Inc. ...
Page 139
... RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 R/W-0 R/W-0 RP8R< ...
Page 140
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for © 2011 Microchip Technology Inc. ...
Page 141
... RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP17R<4:0> R/W-0 R/W-0 R/W-0 RP16R< ...
Page 142
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for © 2011 Microchip Technology Inc. ...
Page 143
... RP25R<4:0>: Peripheral Output Function is Assigned to RP25 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP25R<4:0> R/W-0 R/W-0 R/W-0 RP24R< ...
Page 144
... NOTES: DS70283H-page 144 © 2011 Microchip Technology Inc. ...
Page 145
... SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2011 Microchip Technology Inc. Timer1 also supports these features: • Timer gate operation • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling edge of external gate signal ...
Page 146
... Unimplemented: Read as ‘0’ DS70283H-page 146 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 147
... Timer2 clock and gate inputs are used for the 32-bit timer modules, but an interrupt is generated with the Timer3 interrupt flags. © 2011 Microchip Technology Inc. 12.1 32-bit Operation To configure the Timer2/3 feature timers for 32-bit operation: 1 ...
Page 148
... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70283H-page 148 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2011 Microchip Technology Inc. ...
Page 149
... FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2011 Microchip Technology Inc. 1x Gate Sync Sync TMR2 Comparator PR2 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70283H-page 149 ...
Page 150
... Unimplemented: Read as ‘0’ DS70283H-page 150 U-0 U-0 — — R/W-0 R/W-0 TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 151
... When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), these bits have no effect. © 2011 Microchip Technology Inc. U-0 U-0 (1) — ...
Page 152
... NOTES: DS70283H-page 152 © 2011 Microchip Technology Inc. ...
Page 153
... Mode Select ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2011 Microchip Technology Inc. 1. Simple Capture Event modes: - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin 2 ...
Page 154
... Input capture module turned off DS70283H-page 154 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE HC = Cleared in Hardware U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 155
... TMR3 TMR2 © 2011 Microchip Technology Inc. The Output Compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. The state of the output pin changes when the timer value matches the compare register value ...
Page 156
... OCx Falling edge 1 Current output is maintained OCx Rising and Falling edge OCx Falling edge 0 OCx Falling edge OCxR is zero No interrupt 1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero Timer is reset on period match — © 2011 Microchip Technology Inc. ...
Page 157
... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 158
... NOTES: DS70283H-page 158 © 2011 Microchip Technology Inc. ...
Page 159
... Fault pins to optionally drive each of the PWM output pins to a defined state. Duty cycle updates configurable to be immediate or synchronized to the PWM time base. © 2011 Microchip Technology Inc. 15.1 PWM1: 6-Channel PWM Module This module simplifies the task of generating multiple synchronized PWM outputs ...
Page 160
... Channel 2 Dead-Time Generator 2 PWM Channel 1 Dead-Time Generator 1 Special Event Postscaler SEVTDIR PTDIR PWM1H3 Generator and PWM1L3 Override Logic PWM1H2 Generator and Output PWM1L2 Override Logic Driver PWM1H1 Block Generator and PWM1L1 Override Logic FLTA1 Special Event Trigger © 2011 Microchip Technology Inc. ...
Page 161
... P2FLTACON P2OVDCON P2TMR Comparator P2TPER P2TPER Buffer P2TCON Comparator P2SECMP PWM Time Base © 2011 Microchip Technology Inc. PWM Enable and Mode SFRs Dead-Time Control SFRs Fault Pin Control SFRs PWM Manual Control SFR PWM Generator 1 P2DC1Buffer P2DC1 Comparator Channel 1 Dead-Time ...
Page 162
... U-0 — — — R/W-0 R/W-0 R/W-0 PTCKPS<1:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1:64 prescale) CY (1:16 prescale) CY (1:4 prescale) CY (1:1 prescale) CY U-0 U-0 — — bit 8 R/W-0 R/W-0 PTMOD<1:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 163
... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-0 PTPER<14:0>: PWM Time Base Period Value bits © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PTMR<14:8> R/W-0 R/W-0 R/W-0 PTMR<7:0> Unimplemented bit, read as ‘0’ ...
Page 164
... R/W-0 (2) SEVTCMP<14:8> R/W-0 R/W-0 R/W-0 (2) SEVTCMP<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) TMR<15>) to generate the Special Event Trigger. X TMR<14:0> to generate the Special Event Trigger. X R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 165
... PWMxL pin disabled, I/O pin becomes general purpose I/O Note 1: Reset condition of the PENxH and PENxL bits depends on the value of the PWMPIN Configuration bit in the FPOR Configuration register. 2: PWM2 supports only 1 PWM I/O pin pair. © 2011 Microchip Technology Inc. (2) U-0 U-0 — — ...
Page 166
... Updates from Duty Cycle and Period Buffer registers are enabled DS70283H-page 166 U-0 R/W-0 R/W-0 — SEVOPS<3:0> U-0 U-0 R/W-0 — — IUE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared boundary CY © 2011 Microchip Technology Inc. R/W-0 R/W-0 bit 8 R/W-0 R/W-0 OSYNC UDIS bit Bit is unknown ...
Page 167
... Clock period for Dead-Time Unit Clock period for Dead-Time Unit Clock period for Dead-Time Unit Clock period for Dead-Time Unit bit 5-0 DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 DTB<5:0> R/W-0 ...
Page 168
... PWM2 supports only 1 PWM I/O pin pair. DS70283H-page 168 (1) U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 DTS3I DTS2A DTS2I U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 DTS1A DTS1I bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 169
... PWMxH2/PWMxL2 pin pair is not controlled by Fault Input A bit 0 FAEN1: Fault Input A Enable bit 1 = PWMxH1/PWMxL1 pin pair is controlled by Fault Input PWMxH1/PWMxL1 pin pair is not controlled by Fault Input A Note 1: PWM2 supports only 1 PWM I/O pin pair. © 2011 Microchip Technology Inc. (1) R/W-0 R/W-0 R/W-0 FAOV3L FAOV2H ...
Page 170
... PWM2 supports only 1 PWM I/O pin pair. DS70283H-page 170 (1) R/W-1 R/W-1 R/W-1 POVD3L POVD2H POVD2L R/W-0 R/W-0 R/W-0 POUT3L POUT2H POUT2L U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 POVD1H POVD1L bit 8 R/W-0 R/W-0 POUT1H POUT1L bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 171
... R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC3<15:0>: PWM Duty Cycle 3 Value bits © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PDC1<15:8> R/W-0 R/W-0 R/W-0 PDC1<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 172
... NOTES: DS70283H-page 172 © 2011 Microchip Technology Inc. ...
Page 173
... Existing Pin Logic 0 UPDNx Up/Down 1 © 2011 Microchip Technology Inc. This section describes the Quadrature Encoder Inter- face (QEI) module and associated operational modes. The QEI module provides the interface to incremental encoders for obtaining mechanical position data. The operational features of the QEI include: • ...
Page 174
... Note: The POSCNT register accesses. However, reading the register in Byte mode can result in partially updated values in subsequent reads. Either use Word mode reads/writes, or ensure that the counter is not counting during Byte operations. DS70283H-page 174 allows byte © 2011 Microchip Technology Inc. ...
Page 175
... Position Counter Direction Status Output Enable (QEI logic controls state of I/O pin Position Counter Direction Status Output Disabled (Normal I/O pin operation) bit 5 TQGATE: Timer Gated Time Accumulation Enable bit 1 = Timer gated time accumulation enabled 0 = Timer gated time accumulation disabled © 2011 Microchip Technology Inc. R-0 R/W-0 R/W-0 INDEX UPDN ...
Page 176
... UPDN_SRC: Position Counter Direction Selection Control bit 1 = QEB pin state defines position counter direction 0 = Control/Status bit, UPDN (QEICON<11>), defines timer counter (POSCNT) direction Note: When configured for QEI mode, control bit is a ‘don’t care’. DS70283H-page 176 © 2011 Microchip Technology Inc. ...
Page 177
... Clock Divide 100 = 1:32 Clock Divide 011 = 1:16 Clock Divide 010 = 1:4 Clock Divide 001 = 1:2 Clock Divide 000 = 1:1 Clock Divide bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 R/W-0 — — IMV<1:0> U-0 U-0 — ...
Page 178
... NOTES: DS70283H-page 178 © 2011 Microchip Technology Inc. ...
Page 179
... SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF © 2011 Microchip Technology Inc. The Serial Peripheral Interface (SPI) module is a syn- chronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices can be serial EEPROMs, shift regis- ters, display drivers, analog-to-digital converters, etc. ...
Page 180
... Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. DS70283H-page 180 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...
Page 181
... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 DISSCK DISSDO ...
Page 182
... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. DS70283H-page 182 (3) (3) © 2011 Microchip Technology Inc. ...
Page 183
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 184
... NOTES: DS70283H-page 184 © 2011 Microchip Technology Inc. ...
Page 185
... I C supports multi-master operation, detects bus collision and arbitrates accordingly © 2011 Microchip Technology Inc. 18.1 Operating Modes The hardware fully implements all the master and slave functions of the I specifications, as well as 7-bit and 10-bit addressing. ...
Page 186
... Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2011 Microchip Technology Inc. ...
Page 187
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2011 Microchip Technology Inc. R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
Page 188
... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence 0 = Start condition not in progress DS70283H-page 188 2 C master, applicable during master receive) C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte 2 C master master master) © 2011 Microchip Technology Inc. ...
Page 189
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2011 Microchip Technology Inc. U-0 U-0 — — R/C-0 HSC ...
Page 190
... Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70283H-page 190 2 C slave device address byte. © 2011 Microchip Technology Inc. ...
Page 191
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 192
... NOTES: DS70283H-page 192 © 2011 Microchip Technology Inc. ...
Page 193
... Baud Rate Generator Hardware Flow Control UART Receiver UART Transmitter © 2011 Microchip Technology Inc. The primary features of the UART module are: • Full-Duplex, 8-bit or 9-bit Data Transmission through the UxTX and UxRX pins • Even, Odd or No Parity Options (for 8-bit data) • ...
Page 194
... DS70283H-page 194 MODE REGISTER x R/W-0 R/W-0 U-0 (2) IREN RTSMD R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) R/W-0 R/W-0 — UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 195
... Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2011 Microchip Technology Inc. MODE REGISTER (CONTINUED) x DS70283H-page 195 ...
Page 196
... U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R-0 R-1 (1) UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Clear only bit x = Bit is unknown © 2011 Microchip Technology Inc. ...
Page 197
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for information on enabling the UART module for transmit operation. © 2011 Microchip Technology Inc. STATUS AND CONTROL REGISTER (CONTINUED) x DS70283H-page 197 ...
Page 198
... NOTES: DS70283H-page 198 © 2011 Microchip Technology Inc. ...
Page 199
... Four result alignment options (signed/unsigned, fractional/integer) • Operation during CPU Sleep and Idle modes • 16-word conversion result buffer © 2011 Microchip Technology Inc. The 12-bit ADC configuration supports all the above features, except: • In the 12-bit configuration, conversion speeds 500 ksps are supported. • ...
Page 200
... REF REF 2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. DS70283H-page 200 (1) ( REF REF SS DD VCFG<2:0> ADC1BUF0 ADC1BUF1 ADC1BUF2 V REFH V REFL SAR ADC ADC1BUFE ADC1BUFF © 2011 Microchip Technology Inc. ...