EP20K400CF672C8 Altera, EP20K400CF672C8 Datasheet
EP20K400CF672C8
Manufacturer Part Number
EP20K400CF672C8
Description
APEX 20KC
Manufacturer
Altera
Datasheet
1.EP20K1000CF672C8.pdf
(90 pages)
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Features...
Notes to
(1)
(2)
(3)
Altera Corporation
DS-APEX20KC-2.2
Maximum system gates
Typical gates
LEs
ESBs
Maximum RAM bits
PLLs
Speed grades
Maximum macrocells
Maximum user I/O pins
February 2004 ver. 2.2
Table 1. APEX 20KC Device Features
The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
PLL: phase-locked loop.
The -7 speed grade provides the fastest performance.
(2)
Table
Feature
(3)
1:
■
■
EP20K200C
Programmable logic device (PLD) manufactured using a 0.15-µm all-
layer copper-metal fabrication process
–
–
–
–
–
–
High-density architecture
–
–
–
-7, -8, -9
526,000
200,000
106,496
8,320
832
376
52
25 to 35% faster design performance than APEX
Pin-compatible with APEX 20KE devices
High-performance, low-power copper interconnect
MultiCore
and embedded memory
LUT logic used for register-intensive functions
Embedded system blocks (ESBs) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
200,000 to 1 million typical gates (see
Up to 38,400 logic elements (LEs)
Up to 327,680 RAM bits that can be used without reducing
available logic
2
Note (1)
®
TM
architecture integrating look-up table (LUT) logic
EP20K400C
1,052,000
-7, -8, -9
400,000
212,992
16,640
1,664
104
488
4
EP20K600C
1,537,000
-7, -8, -9
600,000
311,296
24,320
Programmable Logic
2,432
152
588
4
Table
APEX 20KC
1)
TM
EP20K1000C
1,772,000
1,000,000
20KE devices
-7, -8, -9
327,680
38,400
2,560
Data Sheet
160
708
Device
4
1
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