EPF10K100EQC208-1

Manufacturer Part NumberEPF10K100EQC208-1
DescriptionFLEX 10KE
ManufacturerAltera
EPF10K100EQC208-1 datasheets

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Page 41/100

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Table 13. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices
Symbol
Parameter
t
Input rise time
R
t
Input fall time
F
t
Input duty cycle
INDUTY
f
Input clock frequency (ClockBoost
CLK1
clock multiplication factor equals 1)
f
Input clock frequency (ClockBoost
CLK2
clock multiplication factor equals 2)
f
Input deviation from user
CLKDEV
specification in the MAX+PLUS II
(1)
software
t
Input clock stability (measured
INCLKSTB
between adjacent clocks)
t
Time required for ClockLock or
LOCK
ClockBoost to acquire lock
t
Jitter on ClockLock or ClockBoost-
JITTER
(4)
generated clock
t
Duty cycle for ClockLock or
OUTDUTY
ClockBoost-generated clock
Notes to tables:
(1)
To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the
input frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency.
The f
parameter specifies how much the incoming clock can differ from the specified frequency during
CLKDEV
device operation. Simulation does not reflect this parameter.
(2)
Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
(3)
During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the t
(4)
The t
specification is measured under long-term observation. The maximum value for t
JITTER
t
is lower than 50 ps.
INCLKSTB
I/O
Configuration
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Condition
(3)
t
< 100
INCLKSTB
t
< 50
INCLKSTB
value is less than the time required for configuration.
LOCK
This section discusses the peripheral component interconnect (PCI)
pull-up clamping diode option, slew-rate control, open-drain output
option, and MultiVolt I/O interface for FLEX 10KE devices. The PCI
pull-up clamping diode, slew-rate control, and open-drain output options
are controlled pin-by-pin via Altera software logic options. The MultiVolt
I/O interface is controlled by connecting V
V
. Its effect can be simulated in the Altera software via the Global
CCINT
Project Device Options dialog box (Assign menu).
Min
Typ
Max
5
5
40
60
25
75
16
37.5
(2)
25,000
100
10
250
(4)
200
40
50
60
is 200 ps if
JITTER
to a different voltage than
CCIO
Unit
ns
ns
%
MHz
MHz
PPM
ps
µs
ps
ps
%
41

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