EPF10K100EQC208-1

Manufacturer Part NumberEPF10K100EQC208-1
DescriptionFLEX 10KE
ManufacturerAltera
EPF10K100EQC208-1 datasheets

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FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 28. Synchronous Bidirectional Pin External Timing Model
Tables 24
parameters.
parameters and their symbols.
Table 24. LE Timing Microparameters (Part 1 of 2)
Symbol
t
LUT delay for data-in
LUT
t
LUT delay for carry-in
CLUT
t
LUT delay for LE register feedback
RLUT
t
Data-in to packed register delay
PACKED
t
LE register enable delay
EN
t
Carry-in to carry-out delay
CICO
t
Data-in to carry-out delay
CGEN
t
LE register feedback to carry-out delay
CGENR
t
Cascade-in to cascade-out delay
CASC
t
LE register control signal delay
C
t
LE register clock-to-output delay
CO
t
Combinatorial delay
COMB
t
LE register setup time for data and enable signals before clock; LE register
SU
recovery time after asynchronous clear, preset, or load
t
LE register hold time for data and enable signals after clock
H
t
LE register preset delay
PRE
56
OE Register
D
Dedicated
Clock
CLRN
Output Register
D
CLRN
Input Register
D
CLRN
through
28
describe the FLEX 10KE device internal timing
Tables 29
through
30
describe the FLEX 10KE external timing
Note (1)
Parameter
PRN
Q
t
XZBIDIR
t
ZXBIDIR
t
OUTCOBIDIR
PRN
Bidirectional
Q
Pin
t
INSUBIDIR
t
INHBIDIR
PRN
Q
Altera Corporation
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