EPF10K200EBC600-3 Altera, EPF10K200EBC600-3 Datasheet

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... Feature Typical gates (1) Maximum system gates Logic elements (LEs) EABs Total RAM bits Maximum user I/O pins Altera Corporation DS-F10KE-2.5 ® Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device – Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions – ...

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... Open-drain option on each I/O pin – Programmable output slew-rate control to reduce switching noise – Clamp to V user-selectable on a pin-by-pin basis CCIO – Supports hot-socketing EPF10K130E EPF10K200E EPF10K200S 130,000 200,000 342,000 513,000 6,656 9,984 16 24 65,536 98,304 413 470 TM options for reduced clock Altera Corporation ...

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... This option is supported with a 484-pin FineLine BGA package. By using SameFrame pin migration, all FineLine BGA packages are pin-compatible. For example, a board can be designed to support 256-pin, 484-pin, and 672-pin FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration is set. ...

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... General Altera FLEX 10KE devices are enhanced versions of FLEX 10K devices. Based on reconfigurable CMOS SRAM elements, the FLEX architecture Description incorporates all features necessary to implement common gate array megafunctions. With up to 200,000 typical gates, FLEX 10KE devices provide the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device ...

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... Table 6 shows FLEX 10KE performance for more complex designs. These designs are available as Altera MegaCore LEs Used -1 Speed Grade -2 Speed Grade -3 Speed Grade 597 192 1,854 23.4 113 342 36 [points +14 + ceiling] Performance 250 200 ...

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... FLEX 10KE devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers the EPC1, EPC2, and EPC16 configuration devices, which configure FLEX 10KE devices via a serial data stream. ...

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... AHDL), and waveform design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, and device configuration. The Altera software provides EDIF and LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX workstation-based EDA tools ...

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... When used with a dedicated clock pin, these registers provide exceptional performance. As inputs, they provide setup times as low as 0.9 ns and hold times of 0 ns. As outputs, these registers provide clock-to-output times as low as 3.0 ns. IOEs provide a variety of features, such as JTAG BST support, slew-rate control, tri-state buffers, and open-drain outputs. 8 Altera Corporation ...

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... Interconnect Logic Array IOE IOE Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Figure 1 shows a block diagram of the FLEX 10KE architecture. Each group of LEs is combined into an LAB; groups of LABs are arranged into rows and columns. Each row also contains a single EAB. The LABs and EABs are interconnected by the FastTrack Interconnect routing structure ...

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... When in dual-port mode, separate clocks may be used for EAB read and write sections, which allows the EAB to be written and read at different rates. It also has separate synchronous clock enable signals for the EAB read and write sections, which allow independent control of these sections. 10 Altera Corporation ...

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... EPF10K30E and EPF10K50E devices have 88 EAB local interconnect channels; EPF10K100E, EPF10K130E, and EPF10K200E devices have 104 EAB local interconnect channels. Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet The EAB can also be used for bidirectional, dual-port memory applications where two ports read or write simultaneously. To implement this type of dual-port memory, two EABs are used to support two simultaneous read or writes ...

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... FLEX 10KE Embedded Programmable Logic Devices Data Sheet The EAB can also use Altera megafunctions to implement dual-port RAM applications where both ports can read or write, as shown in Figure 3. FLEX 10KE EAB in Dual-Port RAM Mode The FLEX 10KE EAB can be used in a single-port mode, which is useful for ...

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... Clocks 2 EAB Local Interconnect (1) Note: (1) EPF10K30E, EPF10K50E, and EPF10K50S devices have 88 EAB local interconnect channels; EPF10K100E, EPF10K130E, EPF10K200E, and EPF10K200S devices have 104 EAB local interconnect channels. Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Chip-Wide Row Interconnect Reset ...

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... Figure 6. Examples of Combining FLEX 10KE EABs If necessary, all EABs in a device can be cascaded to form a single RAM block. EABs can be cascaded to form RAM blocks 2,048 words without impacting timing. The Altera software automatically combines EABs to meet a designer’s RAM specifications. 14 256 ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet EABs provide flexible options for driving and controlling clock signals. Different clocks and clock enables can be used for reading and writing to the EAB. Registers can be independently inserted on the data input, EAB output, write address, write enable signals, read address, and read enable signals ...

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... EPF10K130E, EPF10K200E, and EPF10K200S devices have 34. 16 Dedicated Inputs & Global Signals Row Interconnect 6 4 Carry-In & Cascade- LE1 4 LE2 4 LE3 4 LE4 4 LE5 4 LE6 4 LE7 4 LE8 terconnect ter Carry-Out & Cascade-Out See Figure 12 for details. Column-to-Row Interconnect terconnect ter Column Interconnect ter terconnect Altera Corporation ...

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... Chip-Wide Reset labctrl3 labctrl4 Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Each LAB provides four control signals with programmable inversion that can be used in all eight LEs. Two of these signals can be used as clocks, the other two can be used for clear/preset control. The LAB clocks can be driven by the dedicated clock input pins, global signals, I/O signals, or internal signals via the LAB local interconnect ...

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... LUT and the next portion of the carry chain. This feature allows the FLEX 10KE architecture to implement high-speed counters, adders, and comparators of arbitrary width efficiently. Carry chain logic can be created automatically by the Altera Compiler during design processing, or manually by the designer during design entry. Parameterized functions such as LPM and DesignWare functions automatically take advantage of carry chains ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Figure 9 shows how an n-bit full adder can be implemented LEs with the carry chain. One portion of the LUT generates the sum of two bits using the input signals and the carry-in signal; the sum is routed to the output of the LE ...

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... LEs delay as low as 0.6 ns per LE, each additional LE provides four more inputs to the effective width of a function. Cascade chain logic can be created automatically by the Altera Compiler during design processing, or manually by the designer during design entry. Cascade chains longer than eight bits are implemented automatically by linking several LABs together ...

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... LE operating mode for optimal performance. The architecture provides a synchronous clock enable to the register in all four modes. The Altera software can set DATA1 to enable the register synchronously, providing easy implementation of fully synchronous designs. ...

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... Carry-Out Cascade-In 3-Input 1 LUT 0 3-Input LUT Carry-Out 3-Input 1 LUT 0 3-Input LUT Carry-Out LE-Out to FastTrack Interconnect PRN D Q LE-Out to Local ENA Interconnect CLRN LE-Out PRN D Q ENA CLRN PRN D Q ENA CLRN Cascade-Out PRN D Q ENA CLRN Cascade-Out LE-Out LE-Out Altera Corporation ...

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... In normal mode, four data inputs from the LAB local interconnect and the carry-in are inputs to a four-input LUT. The Altera Compiler automatically selects the carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT output can be combined with the cascade-in signal to form a cascade chain through the cascade-out signal ...

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... LABCTRL1 implements an asynchronous load. The data to be loaded is driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the register. During compilation, the Altera Compiler automatically selects the best control signal implementation. Because the clear and preset functions are active-low, the Compiler automatically assigns a logic high to an unused clear or preset ...

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... NOT Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet In addition to the six clear and preset modes, FLEX 10KE devices provide a chip-wide reset pin that can reset all registers in the device. Use of this feature is set during design entry. In any of the clear and preset modes, the chip-wide reset overrides all other signals ...

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... Asynchronous Load with Preset When implementing an asynchronous load in conjunction with preset, the Altera software provides preset control by using the clear and inverting the input and output of the register. Asserting LABCTRL2 presets the register, while asserting LABCTRL1 loads the register. The Altera software inverts the signal that drives DATA3 to account for the inversion of the register’ ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet FastTrack Interconnect Routing Structure In the FLEX 10KE architecture, connections between LEs, EABs, and device I/O pins are provided by the FastTrack Interconnect routing structure, which is a series of continuous horizontal and vertical routing channels that traverses the device ...

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... Row Channels Each LE can drive two row channels each intersection, six row channels can drive column channels. Each LE can switch interconnect access with the adjacent LAB. To LAB Local Interconnect Column Channels To Other Columns From Adjacent LAB To Adjacent LAB To Other Rows Altera Corporation ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet For improved routing, the row interconnect consists of a combination of full-length and half-length channels. The full-length channels connect to all LABs in a row; the half-length channels connect to the LABs in half of the row. The EAB can be driven by the half-length channels in the left half of the row and by the full-length channels ...

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... IOE, and the data input and output enable registers should be LE registers placed adjacent to the bidirectional pin. The Altera Compiler uses the programmable inversion option to invert signals from the row and column interconnect automatically where appropriate. ...

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... Dedicated Control Bus Inputs 2 4 Note: (1) All FLEX 10KE devices (except the EPF10K50E and EPF10K200E devices) have a programmable input delay buffer on the input path. Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet 12 VCC Chip-Wide VCC OE[7..0] (1) Programmable Delay VCC CLK[1 ...

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... When the true and complement of a dedicated input drives IOE clocks, two signals on the peripheral control bus are consumed, one for each sense of the clock eight output enable signals Up to six clock enable signals Up to two clock signals Up to two clear signals Altera Corporation ...

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... OE5 CLKENA0/CLK0/GLOBAL0 CLKENA1/OE6/GLOBAL1 CLKENA2/CLR0 CLKENA3/OE7/GLOBAL2 CLKENA4/CLR1 CLKENA5/CLK1/GLOBAL3 Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet When dedicated inputs drive non-inverted and inverted peripheral clears, clock enables, and output enables, two signals on the peripheral control bus will be used. Tables 8 and ...

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... The chip-wide output enable pin is an active-high pin (DEV_OE) that can be used to tri-state all pins on the device. This option can be set in the Altera software. On EPF10K50E and EPF10K200E devices, the built-in I/O pin pull-up resistors (which are active during configuration) are active when the chip-wide output enable pin is asserted ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Row-to-IOE Connections When an IOE is used as an input signal, it can drive two separate row channels. The signal is accessible by all LEs within that row. When an IOE is used as an output, the signal is driven by a multiplexer that selects a signal from the row channels ...

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... FLEX 10KE column-to-IOE interconnect resources. Table 11. FLEX 10KE Column-to-IOE Interconnect Resources Device Channels per Column (n) Column Channels per Pin (m) EPF10K30E EPF10K50E EPF10K50S EPF10K100E EPF10K130E EPF10K200E EPF10K200S Table 11. Each IOE is driven by a m-to-1 multiplexer IOE1 m IOE1 Altera Corporation ...

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... FineLine BGA package. The Altera software provides support to design PCBs with SameFrame pin-out devices. Devices can be defined for present and future use. The Altera software generates pin-outs describing how to lay out a board to take advantage of this migration (see Figure 18. SameFrame Pin-Out Example ...

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... EPF10K200SFC672-1X device supports this circuit. The ClockLock and ClockBoost features in FLEX 10KE devices are enabled through the Altera software. External devices are not required to use these features. The output of the ClockLock and ClockBoost circuits is not available at any of the device pins. ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet ClockLock & ClockBoost Timing Parameters For the ClockLock and ClockBoost circuitry to function properly, the incoming clock must meet certain requirements. If these specifications are not met, the circuitry may not lock onto the incoming clock, which generates an erroneous clock within the device ...

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... Jitter on ClockLock or ClockBoost- JITTER (4) generated clock t Duty cycle for ClockLock or OUTDUTY ClockBoost-generated clock 40 and 13 summarize the ClockLock and ClockBoost parameters Condition (3) t < 100 INCLKSTB t < 50 INCLKSTB Min Typ Max 180 16 90 (2) 25,000 100 10 250 (4) 200 Altera Corporation Unit MHz MHz PPM ps µ ...

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... To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the input frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. The f parameter specifies how much the incoming clock can differ from the specified frequency during CLKDEV device operation ...

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... These devices have one set of V pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). 42 value and are required for 3.3-V PCI compliance. CCIO is CCIO is 2 pin CCIO CC Altera Corporation ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet The VCCINT pins must always be connected to a 2.5-V power supply. With a 2.5-V V level, input voltages are compatible with 2.5-V, 3.3- CCINT V, and 5.0-V inputs. The VCCIO pins can be connected to either a 2.5 ...

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... IDCODE information for FLEX 10KE devices. 44 Table 16. FLEX 10KE Boundary-Scan Register Length Device EPF10K30E EPF10K50E EPF10K50S EPF10K100E EPF10K130E EPF10K200E EPF10K200S TM STAPL Description Boundary-Scan Register Length 690 798 1,050 1,308 1,446 Table 15. Tables 16 and 17 Altera Corporation ...

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... FLEX 10KE devices include weak pull-up resistors on the JTAG pins. For more information, see the following documents: Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) BitBlaster Serial Download Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet Jam Programming & Test Language Specification ...

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... Capture register setup time JSSU t Capture register hold time JSH t Update register clock to output JSCO t Update register high impedance to valid output JSZX t Update register valid output to high impedance JSXZ t t JPSU JPH t JPCO t JSH t t JSCO JSXZ Min 100 Altera Corporation t JPXZ Max Unit ...

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... AMB T Junction temperature J Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Each FLEX 10KE device is functionally tested. Complete testing of each configurable static random access memory (SRAM) bit and all logic functionality ensures 100% yield. AC test measurements for FLEX 10KE ...

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... For industrial use Min Max Unit 2.70 (2.70) V 3.60 (3.60) V 2.70 (2.70) V –0.5 5. CCIO 0 70 ° C –40 85 ° ° C –40 100 ° Min Max Unit 2.625 V (2.625) 3.60 (3.60) V 2.625 V (2.625) –0.5 5. CCIO 0 70 ° C –40 85 ° ° C –40 100 ° Altera Corporation ...

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... I Tri-stated I/O pin OZ leakage current I V supply current CC0 CC (standby) R Value of I/O pin pull- CONF up resistor before and during configuration Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Conditions 1.7, 0 – 3.00 V (9) CCIO I = –0 3.00 V ...

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... Output capacitance OUT Notes to tables: (1) See the Operating Requirements for Altera Devices Data (2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. (3) Numbers in parentheses are for industrial-temperature-range devices. ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Figure 22 shows the required relationship between V 3.3-V PCI compliance. Figure 22. Relationship between V 2.7 V (V) CCINT II 2.5 2.3 3.0 Figure 23 shows the typical output drive characteristics of FLEX 10KE devices with 3.3-V and 2.5 ...

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... LEs between the source and destination LEs 2.5 V CCINT Typical 2 CCIO Output Room Temperature Current (mA Output Voltage ( register clock-to-output delay (t Interconnect delay (t SAMEROW LE look-up table delay (t LE register setup time (t Note ( Room Temperature Output Voltage ( LUT ) 2.5 V CCINT = 3.3 V CCIO Altera Corporation ...

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... Clock/Input Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Timing simulation and delay prediction are available with the Altera Simulator and Timing Analyzer, or with industry-standard EDA tools. The Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post-synthesis timing simulation with 0.1-ns resolution ...

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... Figure 25. FLEX 10KE Device LE Timing Model Carry-In Data-In Control-In 54 Cascade-In LUT Delay t LUT t RLUT t CLUT Packed Register Delay t PACKED Register Control Delay Carry Chain Delay t CGENR t CASC t CGEN t CICO t t LABCARRY LABCASC Carry-Out Cascade-Out Register Delays Data-Out COMB PRE t CLR Altera Corporation ...

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... Delay Input Register Clock t EABCLK Output Register Clock Read Enable Input Delays t EABRE1 RE t EABRE2 Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Output Data I/O Register Delay t IOD I/O Element Contol Delay t IOC Input Register Delay I/O Register t ...

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... Dedicated Clock CLRN Output Register D CLRN Input Register D CLRN through 28 describe the FLEX 10KE device internal timing Tables 29 through 30 describe the FLEX 10KE external timing Note (1) Parameter PRN Q t XZBIDIR t ZXBIDIR t OUTCOBIDIR PRN Bidirectional Q Pin t INSUBIDIR t INHBIDIR PRN Q Altera Corporation Condition ...

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... IOE input pad and buffer to IOE register delay INREG t IOE register feedback delay IOFD t IOE input pad and buffer to FastTrack Interconnect delay INCOMB Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Note (1) Parameter Note (1) Parameter CCIO CCIO CCIO CCIO ...

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... Address hold time with respect to the falling edge of the read enable RAH t Write enable to data output valid delay WO t Data-in to data-out valid delay DD t Data-out delay EABOUT t Clock high time EABCH t Clock low time EABCL 58 Note (1) Parameter Conditions (5) (5) (5) (5) Altera Corporation ...

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... EAB address setup time before rising edge of write pulse when not using EABWASU input registers t EAB address hold time after falling edge of write pulse when not using input EABWAH registers t EAB write enable to data output valid delay EABWO Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Note (1) (6) , Parameter Conditions 59 ...

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... Setup time with global clock for registers used in PCI designs PCISU t Hold time with global clock for registers used in PCI designs PCIH t Clock-to-output delay with global clock for registers used in PCI designs PCICO 60 Note (1) Parameter Parameter Conditions (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) Conditions (8) (9) (9) (9) , (9) (10) (9),(10) , (9) (10) Altera Corporation ...

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... These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing analysis are required to determine actual worst-case performance. (8) Contact Altera Applications for test circuit specifications and test conditions. (9) This timing parameter is sample-tested only. (10) This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local Bus Specification, revision 2 ...

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... Figure 29. EAB Asynchronous Timing Waveforms EAB Asynchronous Read WE Address a0 Data-Out d0 EAB Asynchronous Write WE Data-In t EABWASU a0 Address Data-Out 62 and 30 show the asynchronous and synchronous timing a1 t EABAA d1 t EABWP t EABWDSU din0 t EABWCCOMB a1 din0 Tables EABRCCOMB d2 t EABWDH din1 t EABWAH a2 t EABDD din1 Altera Corporation a3 d3 dout2 ...

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... CLK Data-Out Table 31. EPF10K30E Device LE Timing Microparameters (Part Symbol -1 Speed Grade Min t LUT t CLUT t RLUT t PACKED CICO t CGEN Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet a1 t EABDATAH t EABDATACO din2 a2 t EABDATAH t EABDATASU t EABWCREG dout0 dout1 Tables 31 through 37 show EPF10K30E device internal and external timing parameters ...

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... Speed Grade Min Max 0.2 1.0 0.0 0.5 0.6 0.6 1.3 1.2 1.2 2.5 2.5 Note (1) -3 Speed Grade Min Max 3.8 0.5 1.6 0.0 1.9 0.5 1.6 3.0 2.5 7.0 4.3 4.3 3.8 8.3 5.5 2.4 2.4 Altera Corporation Unit Unit ...

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... WAH t 3.1 RASU t 0.2 RAH EABOUT t 1.5 EABCH t 2.5 EABCL Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 1.7 2.0 0.6 0.7 1.1 1.3 0.4 0.4 0.8 0.9 0.4 0.4 0.0 0.0 0.3 ...

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... Note (1) -3 Speed Grade Unit Min Max 8.8 ns 8.8 ns 6.0 ns 3.3 ns 8.0 ns 9.0 ns 7.7 ns 1.1 ns 2.0 ns 0.0 ns 1.7 ns 0.0 ns 2.0 ns 0.0 ns 4.3 ns 0.4 ns 6.8 ns Altera Corporation ...

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... INSU t (4) 0.0 INH t (4) 0.5 OUTCO t 3.0 PCISU t 0.0 PCIH t 2.0 PCICO Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 1.8 2.4 1.5 1.8 1.5 1.8 2.2 2.6 1.5 1.8 0.1 0.2 2.0 2 ...

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... Notes (1), (2) -3 Speed Grade Unit Min Max 5.2 0.0 – – 2.0 7.6 9.7 9.7 – – – – Note (1) -3 Speed Grade Unit Min Max 1.3 0.8 1.1 0.6 0.9 0.3 0.8 0.3 1.4 0.8 0.9 0.8 0.8 Altera Corporation ...

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... OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 1.0 0.5 0.6 0.5 0.6 2.5 2.5 Note (1) -2 Speed Grade Max Min Max 2.2 2.4 0.3 ...

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... Note (1) -3 Speed Grade Min Max 2.7 0.9 1.8 0.6 1.2 0.6 0.0 0.5 0.8 1.4 0.6 0.5 5.1 3.9 1.5 1.4 0.2 2.7 2.9 5.0 0.3 3.9 3.9 0.8 2.5 3.9 Altera Corporation Unit ...

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... DIN2DATA t DCLK2IOE t DCLK2LE t SAMELAB t SAMEROW t SAMECOLUMN t DIFFROW t TWOROWS t LEPERIPH t LABCARRY t LABCASC Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 6.4 7.6 7.6 5.1 2.9 7.0 7.8 5.7 6.7 0.8 0.9 1.7 0.0 1.4 0.0 1 ...

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... Speed Grade Min Max 13.5 4.3 0.0 2.0 7 Notes (1), (2) -3 Speed Grade Min Max 4.3 0.0 2.0 7.3 10.1 10.1 -3 Speed Grade Min Max 1.5 0.9 1.1 0.5 0.3 0.2 0.7 Altera Corporation Unit Unit Unit ...

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... IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Note (1) -2 Speed Grade Max Min Max 0.1 0.1 0.6 0.9 0.8 1.0 0.6 0.8 0.4 0.5 0.6 0.7 0.8 1.0 ...

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... Max 2.6 0.0 2.6 0.5 0.5 0.0 0.0 0.5 0.2 1.4 0.2 0.5 6.6 4.7 1.7 1.7 0.3 2.8 2.8 5.2 0.2 2.6 2.6 0.3 2.5 4.7 Note (1) -3 Speed Grade Min Max 9.9 9.9 8.5 4.7 Altera Corporation Unit Unit ...

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... DIN2DATA t DCLK2IOE t DCLK2LE t SAMELAB t SAMEROW t SAMECOLUMN t DIFFROW t TWOROWS t LEPERIPH t LABCARRY t LABCASC Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 7.7 7.0 3.4 4.5 0.5 0.7 1.0 0.1 1.4 0.0 1.3 0.2 5.2 0.0 3.4 4 ...

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... Speed Grade Min Max 16.0 3.3 0.0 2.0 9.1 – – – – – – – – Notes (1), (2) -3 Speed Grade Min Max 3.3 0.0 – – 2.0 9.1 10.1 10.1 – – – – Altera Corporation Unit Unit ...

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... IOC t IOCO t IOCOMB t 1.0 IOSU t 0.9 IOH t IOCLR t OD1 t OD2 Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Tables 52 through 58 show EPF10K130E device internal and external timing parameters. -2 Speed Grade Max Min 0.6 0.6 0.7 0.3 0.2 0.1 0.4 ...

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... Max 7.5 5.5 5.5 5.5 7.5 4.1 0.6 0.6 Note (1) -3 Speed Grade Min Max 2.6 0.0 2.6 0.5 0.5 0.0 0.0 0.5 0.2 1.4 0.2 0.5 6.6 4.7 1.7 1.7 0.3 2.8 2.8 5.2 0.2 2.6 Altera Corporation Unit Unit ...

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... EABWESU t 0.0 EABWEH t 1.0 EABWDSU t 0.2 EABWDH t 4.1 EABWASU t 0.0 EABWAH t EABWO Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 1.5 2.0 0.2 0.3 2.0 3.5 -2 Speed Grade Max Min Max 5.9 7.5 7.5 6 ...

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... Note (1) -3 Speed Grade Min Max 4.4 1.6 2.2 2.7 1.6 0.2 5.1 4.4 9.5 14.6 6.9 1.0 1.6 (2) -3 Speed Grade Min Max 16.0 3.0 0.0 2.0 9.2 – – – – – – – – Altera Corporation Unit Unit ...

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... RLUT t PACKED CICO t CGEN t CGENR t CASC COMB t 0.4 SU Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min 2.4 0.0 3.0 0.0 5.0 2.0 5.6 5.6 4.0 0.5 4.6 4.6 Tables 24 through 30 Tables 59 through 65 show EPF10K200E device internal and external timing parameters ...

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... Note (1) -3 Speed Grade Min Max 1.5 0.8 0.8 3.0 3.0 Note (1) -3 Speed Grade Min Max 2.6 0.5 2.6 0.8 1.2 1.1 0.3 0.9 0.7 3.9 7.1 7.1 6.9 10.1 7.7 2.4 2.4 Altera Corporation Unit Unit ...

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... Table 62. EPF10K200E Device EAB Internal Timing Macroparameters (Part Symbol -1 Speed Grade Min t EABAA t 5.1 EABRCOMB t 4.8 EABRCREG t 3.3 EABWP Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 2.0 2.4 0.4 0.5 1.4 1.7 0.0 0 ...

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... Note (1) -3 Speed Grade Unit Min Max 10.7 ns 10.6 ns 6.7 ns 1.3 ns 2.1 ns 0.0 ns 1.5 ns 0.6 ns 2.4 ns 0.0 ns 4.7 ns 0.7 ns 5.8 ns Note (1) -3 Speed Grade Unit Min Max 5.7 ns 2.0 ns 3.0 ns 4.0 ns 2.0 ns 0.2 ns 3.6 ns 4.1 ns 7.7 ns 11.3 ns 9.0 ns 0.2 ns 1.4 ns Altera Corporation ...

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... Table 66. EPF10K50S Device LE Timing Microparameters (Part Symbol -1 Speed Grade Min t LUT t CLUT t RLUT t PACKED CICO t CGEN Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Notes -2 Speed Grade Max Min 10.0 3.4 0.0 4.5 2.0 6.2 0.0 6.0 2.0 -2 Speed Grade Max Min 4 ...

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... Speed Grade Min Max 0.1 1.0 0.8 0.7 0.5 0.7 0.8 0.7 1.2 3.0 3.0 Note (1) -3 Speed Grade Min Max 1.9 0.4 2.6 0.8 1.3 0.6 0.4 1.9 1.7 4.3 7.5 7.5 7.3 9.9 5.6 1.8 1.8 Altera Corporation Unit Unit ...

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... WAH t 1.5 RASU t 0.1 RAH EABOUT t 1.5 EABCH t 1.5 EABCL Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 1.7 2.4 0.4 0.6 1.0 1.4 0.0 0.0 0.0 0.0 0.4 0.6 0.0 0.0 0.8 1 ...

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... Min Max 7.0 ns 7.0 ns 6.6 ns 3.8 ns 8.6 ns 10.6 ns 7.2 ns 1.5 ns 2.1 ns 0.0 ns 1.3 ns 0.8 ns 2.2 ns 0.0 ns 3.0 ns 1.8 ns 5.9 ns Note (1) -3 Speed Grade Unit Min Max 4.6 ns 2.7 ns 5.1 ns 2.6 ns 2.7 ns 0.2 ns 2.4 ns 2.1 ns 4.5 ns 6.9 ns 3.4 ns 0.2 ns 1.3 ns Altera Corporation ...

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... All timing parameters are described in (2) This parameter is measured without use of the ClockLock or ClockBoost circuits. (3) This parameter is measured with use of the ClockLock or ClockBoost circuits Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Note (1) -2 Speed Grade Max Min Max 8 ...

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... Min Max 1.2 ns 0.6 ns 0.9 ns 0.7 ns 0.6 ns 0.3 ns 0.6 ns 0.3 ns 1.2 ns 0.8 ns 0.8 ns 0.8 ns 0.7 ns 1.5 ns 0.8 ns 0.8 ns 3.0 ns 3.0 ns Note (1) -3 Speed Grade Unit Min Max 2.6 ns 0.5 ns 2.6 ns 0.8 ns 1.2 ns 1.1 ns 0.3 ns 0.9 ns 0.4 ns 3.9 ns 7.1 ns 7.1 ns Altera Corporation ...

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... WAH t 1.6 RASU t 0.1 RAH EABOUT t 1.5 EABCH t 2.1 EABCL Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 4.5 4.8 6.6 7.6 3.7 5.7 1.8 3.4 1.8 3.4 -2 Speed Grade Max Min Max 1 ...

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... Unit Min Max 8.4 ns 8.4 ns 7.6 ns 5.3 ns 10.7 ns 10.6 ns 6.7 ns 1.3 ns 2.1 ns 0.0 ns 1.5 ns 0.6 ns 2.4 ns 0.0 ns 4.7 ns 0.7 ns 5.8 ns Note (1) -3 Speed Grade Unit Min Max 5.5 ns 0.9 ns 2.8 ns 2.8 ns 0.9 ns 0.2 ns 5.7 ns 6.4 ns 12.1 ns 17.8 ns 7.2 ns 0.2 ns Altera Corporation ...

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... All timing parameters are described in (2) This parameter is measured without the use of the ClockLock or ClockBoost circuits. (3) This parameter is measured with the use of the ClockLock or ClockBoost circuits. Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max ...

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... LE typically consumes. The P device output load characteristics and switching frequency, can be calculated using the guidelines given in Power for Altera Compared to the rest of the device, the embedded array consumes a negligible amount of power. Therefore, the embedded array can be ignored when calculating supply current. ...

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... Current (mA Frequency (MHz) Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet To better reflect actual designs, the power model (and the constant K in the power calculation equations) for continuous interconnect FLEX devices assumes that LEs drive FastTrack Interconnect channels. In contrast, the power model of segmented FPGAs assumes that all LEs drive only one short interconnect segment ...

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... POR timing information. 96 vs. Operating Frequency (Part EPF10K200E I Current (mA) 100 50 Frequency (MHz) EPF10K200S 600 400 Supply I CC Current (mA) 200 0 600 400 Supply CC 200 0 Frequency (MHz) 100 50 Frequency (MHz) rises, the device initiates a CC 100 50 Altera Corporation ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. Together, the configuration and initialization processes are called command mode ...

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... FLEX 10KE Embedded Programmable Logic Devices Data Sheet Additionally, the Altera software offers several features that help plan for future device migration by preventing the use of conflicting I/O pins. Configuration Schemes The configuration data for a FLEX 10KE device can be loaded with one of five configuration schemes (see application ...

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... History Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. The information contained in the FLEX 10KE Embedded Programmable Logic Data Sheet version 2.5 supersedes information published in previous versions ...

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... Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera 101 Innovation Drive Corporation in the U ...