EPM7064STC100-6 Altera, EPM7064STC100-6 Datasheet
EPM7064STC100-6
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EPM7064STC100-6 Summary of contents
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... FSU t (ns) 4 CO1 f (MHz) 151.5 CNT Altera Corporation DS-MAX7000-6.5 ® High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532 Includes 5 ...
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... Fast input setup times provided by a dedicated path from I/O pin to macrocell registers – Programmable output slew-rate control Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations EPM7160S EPM7192S 3,200 ...
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... MAX 7000S devices The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds 175 ...
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... Parallel expanders Shared expanders Power-saving mode Security bit PCI-compliant devices available Available only in EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices only. The MultiVolt I/O interface is not available in 44-pin packages. EPM7032 All EPM7064 MAX 7000E EPM7096 Devices Altera Corporation All MAX 7000S Devices ...
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... JTAG pins. (2) Perform a complete thermal analysis before committing a design to this device package. For more information, see the Operating Requirements for Altera Devices Data Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000 architecture supports 100% TTL emulation and high-density integration of SSI, MSI, and LSI logic functions ...
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... MAX 7000 devices to be used in mixed-voltage systems. The MAX 7000 family is supported byAltera development systems, which are integrated packages that offer schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)— ...
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... Control I/O pins Block Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The MAX 7000 architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin ...
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... MAX 7000E and MAX 7000S devices. LAB Macrocells to16 6 to16 PIA LAB Macrocells to16 6 to16 6 Output Enables LAB B 6 to16 6 to16 Macrocells I Control Block 6 LAB D 6 to16 6 to16 Macrocells I Control Block 6 Figures 1 Altera Corporation I/O Pins I/O Pins and 2. ...
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... Expander from PIA Product Ter Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Each LAB is fed by the following signals: 36 signals from the PIA that are used for general logic inputs Global controls that are used for secondary register functions ...
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... operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera development software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. 10 shows a MAX 7000E and MAX 7000S device macrocell ...
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... Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Each programmable register can be clocked in three different modes global clock signal. This mode achieves the fastest clock-to- output performance global clock signal and enabled by an active-high clock enable. This mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock ...
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... OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB. 12 Shareable expanders can be shared by any or all macrocells in an LAB. 36 Signals 16 Shared from PIA Expanders ) is incurred when SEXP Figure 5 shows how shareable expanders Product-Term Select Matrix Altera Corporation Macrocell Product-Term Logic Macrocell Product-Term Logic ...
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... Signals 16 Shared from PIA Expanders Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The compiler can allocate up to three sets five parallel expanders automatically to the macrocells that require additional product terms. Each set of five parallel expanders incurs a small, incremental timing delay (t ) ...
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... The I/O control block of MAX 7000E and MAX 7000S devices has six global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins subset of the I/O macrocells. 14 PIA Signals Figure 7 shows how To LAB . Figure 8 shows the I/O CC Altera Corporation ...
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... Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 8. I/O Control Block of MAX 7000 Devices EPM7032, EPM7064 & EPM7096 Devices OE1 OE2 From Macrocell To PIA MAX 7000E & MAX 7000S Devices PIA From Macrocell Fast Input to Macrocell Register To PIA ...
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... Because some in-circuit testers cannot support an adaptive algorithm, Altera offers devices tested with a constant algorithm. Devices tested to the constant algorithm have an “F” suffix in the ordering code. ...
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... Speed/Power Control Output Configuration Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet For more information on using the Jam language, see (Using the Jam Language for ISP & ICR via an Embedded The ISP circuitry in MAX 7000S devices is compatible with IEEE Std. 1532 specification ...
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... Hardware device. f For more information, see the The Altera development system can use text- or waveform-format test vectors created with the Text Editor or Waveform Editor to test the programmed device. For added design verification, designers can perform functional testing to compare the functional behavior of a MAX 7000 device with the results of simulation ...
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... Table 6 describes the JTAG instructions supported by the MAX 7000 family. The pin-out tables (see the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information) show the location of the JTAG control pins for each device. If the JTAG interface is not required, the JTAG pins are available as user I/O pins ...
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... The most significant bit (MSB the left. The least significant bit (LSB) for all JTAG IDCODEs is 1. Boundary-Scan Register Length ( (1) 288 312 360 480 Note (1) IDCODE (32 Bits) Manufacturer’s Identity (11 Bits) 00001101110 00001101110 00001101110 00001101110 00001101110 00001101110 Altera Corporation Tables Bit) ( ...
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... Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 9 shows the timing requirements for the JTAG signals. Figure 9. MAX 7000 JTAG Waveforms TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU gnal o Be ured t JSZX gnal o Be iven ...
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... QFP leads. The Development carrier is used with a prototype development socket and special programming hardware available from Altera. This carrier technology Socket makes it possible to program, test, erase, and reprogram a device without exposing the leads to mechanical stress. ...
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... Junction temperature J t Input rise time R t Input fall time F Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Tables 10 through 15 provide information about absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for 5.0-V MAX 7000 devices. Conditions ...
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... 1.0 MHz 1.0 MHz OUT Min Max 2 0.5 CCINT –0.5 (8) 0.8 2.4 2.4 V – 0.2 CCIO 0.45 0.45 0.2 –10 10 –40 40 Note (13) Min Max 12 12 Note (13) Min Max 15 15 Note (13) Min Max 10 10 Altera Corporation Unit Unit pF pF Unit pF pF Unit pF pF ...
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... MAX 7000 device timing can be analyzed with the Altera software, with a variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in devices have fixed internal delays that enable the designer to determine the worst-case timing of any design. The Altera software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for a device-wide performance evaluation ...
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... LAD Register Control Delay t LAC Shared Expander Delay Input Delay t SEXP Application Note 94 (Understanding MAX 7000 Output Register Delay Delay OD1 t t (2) H OD2 t t PRE OD3 t t CLR (2) COMB (1) FSU Fast t ( Figure 13 shows the internal timing Altera Corporation I/O Delay ...
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... Inputs are driven for a logic high and 0 V for a logic low. All timing characteristics are measured at 1.5 V. Shared Expander Parallel Expander (Logic Array Output) Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Combinatorial Mode t IN Input Pin t IO I/O Pin ...
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... Note (1) -7 Speed Grade Max Min Max 6.0 7.5 6.0 7.5 6.0 0.0 3.0 0.5 4.0 4.5 3.0 3.0 3.0 2.0 6.5 7.5 3.0 3.0 3.0 1.0 6.6 8.0 125.0 6.6 8.0 125.0 166.7 Altera Corporation Unit MHz ns MHz MHz ...
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... IC t Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Conditions (2) ( 5.0 V CCIO (7) = 3.3 V CCIO ( 5.0 V CCIO (7) = 3.3 V ...
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... Speed Grade Unit MAX 7000E (-10) Max Min Max 10.0 10.0 ns 10.0 10.0 ns 8.0 ns 0.0 ns 3.0 ns 0 4.0 ns 4.0 ns 3.0 ns 3.0 ns 10.0 10.0 ns 4.0 ns 4.0 ns 4.0 ns 1.0 ns 10.0 10.0 ns 100.0 MHz 10.0 10.0 ns 100.0 MHz 125.0 MHz Altera Corporation ...
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... Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Note (1) Conditions MAX 7000E (-10P) MAX 7000 (-10) Min ( ...
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... Speed Grade Unit MAX 7000 (-12) MAX 7000E (-12) Max Min Max 12.0 12.0 ns 12.0 12.0 ns 10.0 ns 0.0 ns 3.0 ns 0.0 ns 6.0 6.0 ns 4.0 ns 4.0 ns 4.0 ns 4.0 ns 12.0 12.0 ns 5.0 ns 5.0 ns 5.0 ns 1.0 ns 11.0 11.0 ns 90.9 MHz 11.0 11.0 ns 90.9 MHz 125.0 MHz Altera Corporation ...
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... IC t Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Note (1) Conditions MAX 7000E (-12P) Min ( ...
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... Altera Corporation Unit MHz ns MHz MHz ...
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... Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Conditions -15 Min Max 2.0 2.0 (2) 2.0 8.0 1.0 6.0 6.0 (2) 3 ...
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... Figure 13 for more parameter LPA Unit -10 10.0 ns 10.0 ns 7.0 ns 0.0 ns 3.0 ns 0.5 ns 5.0 ns 4.0 ns 4.0 ns 2.0 ns 3.0 ns 10.0 ns 4.0 ns 4.0 ns 4.0 ns 1.0 ns 10.0 ns 100.0 MHz 10.0 ns Altera Corporation ...
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... Array clock delay IC t Register enable time EN t Global control delay GLOB t Register preset time PRE Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Conditions -5 Min Max Min Max Min Max Min Max (4) 175.4 142.9 (5) 250.0 200.0 Note (1) Conditions ...
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... Unit -10 Min Max 3.0 ns 1.0 ns 11.0 ns Figure 13 for more parameter LPA Unit -10 10.0 ns 10.0 ns 7.0 ns 0.0 ns 3.0 ns 0.5 ns 5.0 ns 4.0 ns 4.0 ns 2.0 ns Altera Corporation ...
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... Output buffer enable delay ZX2 t Output buffer enable delay ZX3 t Output buffer disable delay XZ t Register setup time SU Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Conditions -5 Min Max Min Max Min Max Min Max 1 5.4 2.5 2.5 (2) 2.5 ...
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... Table 11. See parameter into the signal LAD , t , and t parameters for macrocells SEXP ACL CPPW Altera Corporation Unit -10 3.0 ns 3.0 ns 0.5 ns 2.0 ns 2.0 ns 5.0 ns 5.0 ns 1.0 ns 3.0 ns 3 ...
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... Minimum array clock period ACNT f Maximum internal array clock ACNT frequency f Maximum clock frequency MAX Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Tables 28 and 29 show the EPM7128S AC operating conditions. Note (1) Conditions -6 Min Max Min Max Min Max Min Max ...
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... Altera Corporation Unit 2.0 ns 2.0 ns 2.0 ns 8.0 ns 1.0 ns 6.0 ns 6.0 ns 3.0 ns 4.0 ns 5.0 ns 8 ...
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... Output data hold time after ODH clock t Minimum global clock period CNT f Maximum internal global clock CNT frequency Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet = 3.3 V 10% for commercial and industrial use LAD LAC IC EN Tables 30 ...
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... Altera Corporation Unit 13.0 ns MHz MHz Unit 2.0 ns 2.0 ns 2.0 ns 8.0 ns 1.0 ns 6.0 ns 6.0 ns 3 ...
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... Global clock hold time of fast FH input t Global clock to output delay CO1 t Global clock high time CH Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Conditions -6 Min Max Min Max Min Max Min Max (7) (8) = 3.3 V 10% for commercial and industrial use. ...
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... Altera Corporation Unit Max 15 13.0 ns MHz 13.0 ns MHz MHz Unit Max 2.0 ns 2 ...
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... PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these devices, add an additional 0 the PIA timing value. (8) The t parameter must be added to the t LPA running in the low-power mode. Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Conditions Min 1.1 1.7 2 ...
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... Altera Corporation Unit MHz ns MHz MHz ...
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... Array clock delay IC t Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Note (1) Conditions -7 Min ( ( 1.1 1.6 2.4 0.6 (7) ...
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... Supply power (P) versus frequency (f is calculated with the following equation: Consumption The P and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera The I application logic, is calculated with the following equation The parameters in this equation are shown below: ...
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... Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Table 36. MAX 7000 I Equation Constants CC Device EPM7032 EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S This calculation provides an I using a pattern of a 16-bit, loadable, enabled, up/down counter in each LAB with no output load ...
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... MAX 7000 EPM7064 151.5 MHz High Speed Typical I Active (mA) 100 150 200 125 MHz High Speed 5 300 Room Temperature 200 CC 60.2 MHz 100 Low Power 0 50 100 Frequency (MHz) Altera Corporation 151.5 MHz High Speed 150 200 ...
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... Room Temperature 400 300 Typical I CC Active (mA) 43.5 MHz 200 Low Power 100 Frequency (MHz) Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet EPM7160E 125 MHz Typical I CC Active (mA) High Speed 150 200 EPM7256E 90.9 MHz High Speed Typical I ...
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... Active (mA) 100 150 200 Room Temperature 120 100 80 CC High Speed 60 56.5 MHz 40 Low Power 100 Frequency (MHz 5 Room Temperature High Speed 180 CC 120 56.5 MHz 60 Low Power 0 50 100 Frequency (MHz) 175.4 MHz 200 149.3 MHz 200 Altera Corporation ...
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... MAX 7000 Programmable Logic Device Family Data Sheet EPM7256S 125.0 MHz High Speed Typical I Active (mA) 55.6 MHz Low Power 75 100 125 Frequency (MHz) See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information 5 Room Temperature 200 56.2 MHz Low Power ...
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... EPM7032S 13 EPM7064 14 I/O EPM7064S 15 VCC 16 I 44-Pin PLCC Pin 34 I/O I/O/(TDO) (2) I/O I/O VCC I/O I/O I/O/(TCK) (2) I/O GND I/O Pin 23 Altera Corporation 39 I/O 38 I/O/(TDO) (2) 37 I/O 36 I/O 35 VCC 34 I/O 33 I/O 32 I/O/(TCK) (2) 31 I/O 30 GND 29 I/O ...
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... Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Figure 17. 68-Pin Package Pin-Out Diagram Package outlines not drawn to scale. I/O 10 VCCIO 11 (2) I/O/(TDI) 12 I/O 13 I/O 14 I/O 15 GND 16 I/O 17 I/O 18 (2) I/O/(TMS) 19 I/O 20 VCCIO 21 I/O 22 I/O 23 I/O 24 I/O 25 GND ...
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... EPM7128E I/O 25 EPM7128S VCCIO 26 I/O 27 EPM7160E I/O 28 I/O 29 EPM7160S I/O 30 I/O 31 GND 32 84-Pin PLCC 74 I/O 73 I/O 72 GND (3) 71 I/O/(TDO) 70 I/O 69 I/O 68 I/O 67 I/O 66 VCCIO 65 I/O 64 I/O 63 I/O (3) 62 I/O/(TCK) 61 I/O 60 I/O 59 GND 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O Altera Corporation ...
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... K EPM7192E J H Bottom View 160-Pin PGA Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet Pin 81 Pin 1 Pin 51 Pin 26 Pin 1 Pin 41 Pin 76 EPM7064S EPM7128S EPM7160S Pin 51 100-Pin TQFP EPM7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E 160-Pin PQFP Pin 121 Pin 81 ...
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... MAX 7000 Programmable Logic Device Family Data Sheet Figure 21. 192-Pin Package Pin-Out Diagram Package outline not drawn to scale. Figure 22. 208-Pin Package Pin-Out Diagram Package outline not drawn to scale. Pin 1 Pin EPM7256E K Bottom J View 192-Pin PGA EPM7256E EPM7256S 208-Pin PQFP/RQFP Pin 157 Pin 105 Altera Corporation ...
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... Revision History Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet The information contained in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.5 supersedes information published in previous versions. The following changes were made in the MAX 7000 Programmable Logic Device Family Data Sheet version 6.5: Version 6 ...
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... Copyright © 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the (408) 544-7000 stylized Altera logo, specific device designations, and all other words and logos that are identified as http://www.altera.com trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Applications Hotline: Corporation in the U ...