EVAL-AD5245EBZ Analog Devices Inc, EVAL-AD5245EBZ Datasheet - Page 14

• Manufacturer Part Number: EVAL-AD5245EBZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5245EBZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5245
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A to B. Unlike the polarity of V
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
If ignoring the effect of the wiper resistance for approximation,
then connecting the A terminal to 5 V and the B terminal to
ground produces an output voltage at the wiper-to-B starting at
0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across Terminal A and B divided by the 256
positions of the potentiometer divider. The general equation
defining the output voltage at V
valid input voltage applied to Terminals A and B is
A more accurate calculation, which includes the effect of wiper
resistance, V
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, R
values. Therefore, the temperature drift reduces to 15 ppm/°C.
ESD PROTECTION
All digital inputs are protected with a series of input resistors and
parallel Zener ESD structures, shown in Figure 38 and Figure 39.
This applies to the digital input pins SDA, SCL, and AD0.
(
(
)
)
W
Figure 39. ESD Protection of Resistor Terminals
=
=
Figure 37. Potentiometer Mode Configuration
, is
256
Figure 38. ESD Protection of Digital Pins
(
V
)
+
I
A, B, W
GND
GND
256
340Ω
256
+
A
B
−
DD
W
W
LOGIC
(
with respect to ground for any
to GND, which must be
WA
)
and R
V
O
WB
, not the absolute
Rev. B | Page 14 of 20
(3)
(4)
TERMINAL VOLTAGE OPERATING RANGE
The AD5245 V
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on Terminals A, B, and W that
exceed V
diodes (see Figure 40).
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminals A, B, and W (see Figure 40), it is important to
power V
A, B, and W; otherwise, the diode is forward biased such that
V
user’s circuit. The ideal power-up sequence is in the following
order: GND, V
relative order of powering V
not important as long as they are powered after V
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disk or chip ceramic
capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum
or electrolytic capacitors should also be applied at the supplies
to minimize any transient disturbance and low frequency ripple
(see Figure 41). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
DD
is powered unintentionally and can affect the rest of the
Figure 40. Maximum Terminal Voltages Set by V
DD
DD
V
and GND before applying any voltage to Terminals
or GND are clamped by the internal forward-biased
DD
DD
DD
10µF
, digital inputs, and then V
Figure 41. Power Supply Bypassing
and GND power supply defines the boundary
C3
+
0.1µF
C1
A
, V
B
, V
V
DD
W
, and the digital inputs is
AD5245
V
A
W
B
GND
DD
A
, V
GND
DD
B
, and V
and GND
DD
and GND.
W
. The