EVAL-AD5252EBZ Analog Devices Inc, EVAL-AD5252EBZ Datasheet - Page 20

• Manufacturer Part Number: EVAL-AD5252EBZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5252EBZ

• Main Purpose: Digital Potentiometer
• Utilized Ic / Part: AD5252
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5251/AD5252
I
The first byte of the AD5251/AD5252 is a slave address byte
(see Figure 33 and Figure 34). It has a 7-bit slave address and an
R/ W bit. The 5 MSB of the slave address is 01011, and the next
2 LSB is determined by the states of the AD1 and AD0 pins.
AD1 and AD0 allow the user to place up to four
AD5251/AD5252 devices on one bus.
AD5251/AD5252 can be controlled via an I
bus and are connected to this bus as slave devices. The 2-wire
I
1.
2.
2
2
C serial bus protocol (see Figure 33 and Figure 34) follows:
C-COMPATIBLE 2-WIRE SERIAL BUS
The master initiates a data transfer by establishing a start
condition, such that SDA goes from high to low while SCL
is high (see Figure 33). The following byte is the slave address
byte, which consists of the 5 MSB of a slave address defined
as 01011. The next two bits are AD1 and AD0, I
address bits. Depending on the states of their AD1 and
AD0 bits, four AD5251/AD5252 devices can be addressed
on the same bus. The last LSB, the R/ W bit, determines
whether data is read from or written to the slave device.
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is called an acknowledge bit). At
this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to or read
from its serial register.
In the write mode (except when restoring EEMEM to the
RDAC register), there is an instruction byte that follows
the slave address byte. The MSB of the instruction byte is
labeled CMD/ REG . MSB = 1 enables CMD, the command
instruction byte; MSB = 0 enables general register writing.
The third MSB in the instruction byte, labeled EE/ RDAC ,
is true when MSB = 0 or when the device is in general
writing mode. EE enables the EEMEM register, and REG
enables the RDAC register. The 5 LSB, A4 to A0, designates
START BY
MASTER
SCL
SDA
1
0
START BY
MASTER
1
SLAVE ADDRESS BYTE
SCL
SDA
0
FRAME 1
1
1 AD1 AD0 R/W
1
0
1
SLAVE ADDRESS BYTE
2
0
C-compatible serial
FRAME 1
1
ACK. BY
AD525x
9
1
2
C device
1
X
Figure 33. General I
Figure 34. General I
AD1 AD0
X
Rev. B | Page 20 of 28
X
INSTRUCTION BYTE
R/W
ACK. BY
AD525x
X
FRAME 2
9
X
2
D7
2
C Write Pattern
1
C Read Pattern
X
3.
4.
D6
X
D5
the addresses of the EEMEM and RDAC registers (see
Figure 27
device is in CMD mode, the four bits following the MSB
are C3 to C1, which correspond to 12 predefined EEMEM
controls and quick commands; there are also four factory-
reserved commands. The 3 LSB—A2, A1, and A0—are
addresses, but only 001 and 011 are used for RDAC1 and
RDAC3, respectively (see
the instruction byte, the last byte in the write mode is the
data byte. Data is transmitted over the serial bus in
sequences of nine clock pulses (eight data bits followed by
an acknowledge bit). The transitions on the SDA line must
occur during the low period of SCL and remain stable
during the high period of SCL (see
In current read mode, the RDAC0 data byte immediately
follows the acknowledgment of the slave address byte.
After an acknowledgement, RDAC1 follows, then RDAC2,
and so on. (There is a slight difference in write mode,
where the last eight data bits representing RDAC3 data are
followed by a no acknowledge bit.) Similarly, the
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 34). Another reading method, random
read method, is shown in Figure 30.
When all data bits have been read or written, a stop
condition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line that
occurs while SCL is high. In write mode, the master pulls
the SDA line high during the 10
stop condition (see Figure 33). In read mode, the master
issues a no acknowledge for the ninth clock pulse, that is,
the SDA line remains high. The master brings the SDA line
low before the 10
line high to establish a stop condition (see Figure 34).
X
RDAC REGISTER
ACK. BY
AD525x
D4
9
FRAME 2
D3
D7 D6 D5
1
and
D2
Figure 28
D1
th
DATA BYTE
D4 D3 D2 D1
D0
FRAME 1
clock pulse and then brings the SDA
NO ACK. BY
MASTER
9
). When MSB = 1 or when the
Figure 31
STOP BY
MASTER
th
D0
clock pulse to establish a
Figure 33
ACK. BY
AD525x
). After acknowledging
9
STOP BY
MASTER
).