EVAL-AD5262EBZ Analog Devices Inc, EVAL-AD5262EBZ Datasheet - Page 15

• Manufacturer Part Number: EVAL-AD5262EBZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5262EBZ

• Main Purpose: Digital Potentiometer
• Utilized Ic / Part: AD5262
• Primary Attributes: Dual Channel, 256 Positions
• Secondary Attributes: SPI Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
The AD5260/AD5262 provide a single- or dual-channel, 256-
position, digitally controlled variable resistor (VR) device and
operate up to 15 V maximum voltage. Changing the programmed
VR settings is accomplished by clocking an 8-/9-bit serial data
word into the SDI (serial data input) pin. For the AD5262, the
format of this data word is one address bit. A0 represents the
first bit, B8, followed by eight data bits, B7 to B0, with MSB
first. Table 2 and Table 3 provide the serial register data word
format. See Table 7 for the AD5262 address assignment to decode
the location of the VR latch receiving the serial register data in
Bit B7 through Bit B0. VR outputs can be changed one at a time
in random sequence. The AD5260/AD5262 preset to a midscale,
simplifying fault condition recovery at power-up. Midscale can
also be achieved at any time by asserting the PR pin. Both parts
have an internal power-on preset that places the wiper in a
midscale preset condition at power-on. Operation of the power-
on preset function depends only on the state of the V
The AD5260/AD5262 contain a power shutdown SHDN pin
that places the RDAC in an almost zero power consumption
state where Terminals Ax are open circuited and the Wiper W
is connected to B, resulting in only leakage currents being con-
sumed in the VR structure. In the shutdown mode, the VR latch
settings are maintained so that, when returning to operational
mode from power shutdown, the VR settings return to their
previous resistance values.
Table 7. AD5262 Address Decode Table
A0
0
1
DIGITAL INTERFACING
The AD5260/AD5262 contain a 4-wire SPI-compatible digital
interface (SDI, SDO, CS , and CLK). For the AD5260, the 8-bit
serial word must be loaded with the MSB first. The format of
the word is shown in
word must be loaded with Address Bit A0 first, then the MSB
of the data. The format of the word is shown in
Latch Loaded
RDAC1
RDAC2
Table 2
. For the AD5262, the 9-bit serial
Table 3
L
pin.
.
Rev. A | Page 15 of 24
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register. Stand-
ard logic families work well. If mechanical switches are used for
product evaluation, they should be debounced by a flip-flop or
other suitable means. Figure 47 shows more detail of the inter-
nal digital circuitry. When CS is low, the clock loads data into
the serial input register on each positive clock edge (see
Table 8. Truth Table
CLK
Low
↑
X
X
X
X
X
1
The data setup and data hold times in Table 1 determine the
data valid time requirements. The AD5260 uses an 8-bit serial
input data register word that is transferred to the internal
RDAC register when the CS line returns to logic high. For the
AD5262, the last nine bits of the data word entered into the
serial register are held when CS returns high. Any extra bits are
ignored. At the same time CS goes high, it gates the address
decoder, enabling one of two positive edge-triggered AD5262
RDAC latches (see
↑
SDO
GND
CLK
= positive edge, X = don’t care, SR = shift register.
SDI
CS
PR
V
L
CS
Low
Low
↑
High
X
High
High
POWER-
PRESET
REG
SER
ON
A0
D7
D6
D5
D4
D3
D2
D1
D0
PR
High
High
High
High
Low
↑
High
Figure 47. AD5262 Block Diagram
Figure 48
ADDR
DEC
EN
1
SHDN
High
High
High
Low
High
High
High
).
Latches all RDAC latches to 0x80.
Register Activity
No SR effect, enables SDO pin.
Shift one bit in from the SDI pin.
The eighth previously entered
bit is shifted out of the SDO pin.
Load SR data into RDAC latch.
No operation.
Sets all RDAC latches to half
scale, wiper centered, and SDO
latch cleared.
Open circuits all Resistor A
terminals, connects W to B, and
turns off SDO output transistor.
LATCH
LATCH
AD5260/AD5262
RDAC
RDAC
PR
PR
1
2
Table 8
V
V
A1
W1
B1
A2
W2
B2
SHDN
SS
DD
).