EVAL-AD5262EBZ Analog Devices Inc, EVAL-AD5262EBZ Datasheet - Page 18

• Manufacturer Part Number: EVAL-AD5262EBZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5262EBZ

• Main Purpose: Digital Potentiometer
• Utilized Ic / Part: AD5262
• Primary Attributes: Dual Channel, 256 Positions
• Secondary Attributes: SPI Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5260/AD5262
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ a compact, minimum lead length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 μF to 0.1 μF disc or
chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance (see Figure 55). Note that
the digital ground should also be joined remotely to the analog
ground to minimize the ground bounce.
TERMINAL VOLTAGE OPERATING RANGE
The AD5260/AD5262 positive V
supply defines the boundary conditions for proper 3-terminal
digital potentiometer operation. Supply signals present on the
A, B, and W terminals that exceed V
the internal forward-biased diodes (see Figure 56).
The ground pin of the AD5260/AD5262 device is primarily
used as a digital ground reference, which needs to be tied to the
common ground of the PCB. The digital input control signals to
the AD5260/AD5262 must be referenced to the device ground
pin (GND), and must satisfy the logic level defined in Table 1.
An internal level shift circuit ensures that the common-mode
Figure 56. Maximum Terminal Voltages Set by V
V
V
DD
SS
Figure 55. Power Supply Bypassing
C3
C4
+
10µF
+
10µF
C1
C2
0.1µF
0.1µF
DD
and negative V
DD
or V
V
V
DD
SS
SS
are clamped by
GND
V
A
W
B
V
DD
DD
SS
and V
SS
power
SS
Rev. A | Page 18 of 24
voltage range of the three terminals extends from V
regardless of the digital input level.
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 56), it is
important to power V
the A, B, and W terminals. Otherwise, the diode becomes forward
biased such that V
affect the rest of the user’s circuit. The ideal power-up sequence
is in the following order: GND, V
and V
inputs is not important as long as they are powered after V
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the −3 dB bandwidth of the AD5260
(20 kΩ resistor) measures 310 kHz at half scale. Figure 28 provides
the large signal Bode plot characteristics of the three available
resistor versions 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic simula-
tion model is shown in Figure 57. The following section provides a
macro model net list for the 20 kΩ RDAC.
MACRO MODEL NET LIST FOR RDAC
PARAM D=256, RDAC=20E3
*
SUBCKT DPOT (A,W,B)
*
CA
RWA
CW
RWB
CB
*
.ENDS DPOT
A
/V
Figure 57. RDAC Circuit Simulation Model for RDAC 20 kΩ
B
/V
W
. The order of powering V
A
A
W
W
B
DD
25pF
/V
A
DD
C
SS
A
/V
are powered unintentionally and may
0
W
0
B
0
SS
RDAC
first before applying any voltage to
20kΩ
W
55pF
C
W
DD
, V
25E-12
{(1-D/256)*RDAC+60}
55E-12
{D/256*RDAC+60}
25E-12
C
25pF
SS
B
, V
B
A
/V
L
, the digital inputs,
B
/V
W
and the digital
SS
to V
DD
/V
DD
SS
.