EVAL-AD5263EBZ Analog Devices Inc, EVAL-AD5263EBZ Datasheet - Page 16

• Manufacturer Part Number: EVAL-AD5263EBZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5263EBZ

• Main Purpose: Digital Potentiometer
• Embedded: No
• Utilized Ic / Part: AD5263
• Primary Attributes: 4 Channel, 256 Position
• Secondary Attributes: I²C & SPI Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5263
I
The word format maps in this section use the following abbreviations.
Abbreviation
S
P
A
AD1, AD0
A1, A0
RS
SD
O1, O2
W
R
D7, D6, D5, D4, D3,
D2, D1, D0
X
I
S
I
S
START BY
2
2
2
MASTER
SCL
S
C WRITE MODE DATA-WORD FORMAT
C READ MODE DATA-WORD FORMAT
C-COMPATIBLE DIGITAL INTERFACE (DIS = 1)
DA
0
SDA
SCL
0
1
1
0
P
Slave Address Byte
0
1
t
1
1
SLAVE ADDRESS BYTE
0
START BY
1
MASTER
S
1
SDA
SCL
Description
Start condition.
Stop condition.
Acknowledge.
I
RDAC channel select.
Software reset wiper (A1, A0) to midscale position.
Shutdown active high; ties wiper (A1, A0) to Terminal A, opens Terminal B, RDAC register contents are not disturbed.
To exit shutdown, the command SD = 0 must be executed for each RDAC (A1, A0).
Data to digital output pins, Pin O1 and Pin O2 in I
determined by V
Write = 0.
Read = 1.
Data bits.
Don’t care.
FRAME 1
2
C device address bits. Must match with the logic states at Pin AD1 and Pin AD0. Refer to Figure 49.
0
1
Slave Address Byte
AD1
t
2
1
1
AD0
1
1
0
t
3
AD1
AD1 AD0 R/W
Figure 44. Reading Data from a Previously Selected RDAC Register in Write Mode
1
W
L
and the logic low level is GND.
SLAVE ADDRESS BYTE
0
t
8
A
t
8
AD0
FRAME 1
1
X
t
ACK BY
AD5263
9
9
1
A1
Figure 43
Figure 42. Detailed I
AD1 AD0 R/W
X
1
R
A0
A1
Instruction Byte
t
t
. Writing to the RDAC Register
9
4
A
Rev. B | Page 16 of 28
RS
INSTRUCTION BYTE
A0
FRAME 1
ACK BY
AD5263
RS
SD
D7
9
2
2
SD
C Timing Diagram
C mode, used to drive external logic. The logic high level is
O1
D7
1
t
D8
7
O1
D6
O2
O2
D5
X
RDAC REGISTER
D5
X
D4
FRAME 2
ACK BY
AD5263
A
S
9
D3
D4
D7
t
5
D7
Data Byte
1
D2
D6
D6
D3
D1
t
2
D5
D5
D0
DATABYTE
NO ACK
BY MASTER
FRAME 1
D4
D2
Data Byte
D4
9
D3
STOP BY
MASTER
D3
D2
D1
D2
D1
D0
D0
D1
ACK BY
AD5263
9
D0
STOP BY
MASTER
P
A
t
10
A
P
P