EVAL-AD5270SDZ Analog Devices Inc, EVAL-AD5270SDZ Datasheet - Page 21

• Manufacturer Part Number: EVAL-AD5270SDZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5270SDZ

• Main Purpose: Digital Potentiometer
• Embedded: No
• Utilized Ic / Part: AD5270
• Primary Attributes: 1 Channel, 1024 Position
• Secondary Attributes: 2.7 ~ 5.5 V, 5 ppm/°C, SPI Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 15. Memory Map
Command Number
5
1
SDO PIN AND DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes: it can be
used to read the contents of the wiper setting and 50-TP values
using Command 2 and Command 5, respectively (see Table 11),
or the SDO pin can be used in daisy-chain mode. Data is clocked
out of SDO on the rising edge of SCLK. The SDO pin contains
an open-drain N-channel FET that requires a pull-up resistor.
To place the pin in high impedance and mini-mize the power
dissipation when the pin is used, the 0x8001 data word followed
by Command 0 should be sent to the part. Table 16 provides a
sample listing for the sequence of the serial data input (DIN).
Daisy chaining minimizes the number of port pins required
from the controlling IC. As shown in Figure 44, the user must
tie the SDO pin of one package to the DIN pin of the next
package. The user may need to increase the clock period because
the pull-up resistor and the capacitive loading at the SDO-to-
DIN interface may require additional time delay between
subsequent devices. When two AD5270/AD5271 devices are
daisy-chained, 32 bits of data are required. The first 16 bits go to
U2, and the second 16 bits go to U1.
Table 16. Minimize Power Dissipation at the SDO Pin
DIN
0xXXXX
0x8001
0x0000
1
Keep the SYNC pin low until all 32 bits are clocked to their
respective serial registers. The SYNC pin is then pulled high to
complete the operation.
X is don’t care.
X is don’t care.
SDO
0xXXXX
0xXXXX
High
Impedance
1
Action
Last user command sent to the digipot.
Prepares the SDO pin to be placed in
high impedance mode.
The SDO pin is placed in high
impedance.
D9
X
X
X
X
X
…
X
X
X
X
X
D8
X
X
X
X
X
…
X
X
X
X
X
D7
X
X
X
X
X
…
X
X
X
X
X
D6
0
0
0
0
0
…
0
0
0
0
0
Data Byte[DB9:DB8]
D5
0
0
0
0
0
0
0
0
1
1
…
D4
0
0
0
0
0
…
0
1
1
0
1
Rev. E | Page 21 of 24
D3
0
0
0
0
0
…
1
0
1
1
0
1
D2
0
0
0
0
1
…
0
1
1
0
0
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices has patented
the RDAC segmentation architecture for all the digital potentio-
meters. In particular, the AD5270/AD5271 employ a three-stage
segmentation approach as shown in Figure 45.The AD5270/
AD5271 wiper switch is designed with the transmission gate
CMOS topology.
SCLK
0
1
1
0
1
0
1
0
1
D1
0
…
ADDRESS
DECODER
8-/10-BIT
µC
MOSI
D0
0
1
0
1
0
…
0
0
0
0
0
Figure 44. Daisy-Chain Configuration Using SDO
SS
Figure 45. Simplified RDAC Circuit
Reserved
1st programmed wiper location (0x01)
2nd programmed wiper location (0x02)
3rd programmed wiper location (0x03)
4th programmed wiper location (0x04)
10th programmed wiper location (0xA)
20th programmed wiper location (0x14)
30th programmed wiper location (0x1E)
40th programmed wiper location (0x28)
50th programmed wiper location (0x32)
Register Contents
…
DIN
SYNC
A
AD5270/
AD5271
U1
SCLK
SDO
R
R
L
L
V
DD
R
2.2kΩ
P
AD5270/AD5271
R
R
R
R
M
M
W
W
DIN
SYNC
AD5270/
AD5271
S
W
U2
SCLK
SDO
W