EVAL-AD5272SDZ Analog Devices Inc, EVAL-AD5272SDZ Datasheet - Page 10

• Manufacturer Part Number: EVAL-AD5272SDZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5272SDZ

• Main Purpose: Digital Potentiometer
• Embedded: No
• Utilized Ic / Part: AD5272
• Primary Attributes: 1 Channel, 1024 Position
• Secondary Attributes: 2.7 ~ 5.5 V, 5 ppm/°C, I²C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5272/AD5274
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 10. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
EPAD
Mnemonic
V
A
W
V
EXT_CAP
GND
RESET
SDA
SCL
ADDR
Exposed Pad
(LFCSP Only)
DD
SS
EXT_CAP
Figure 4. MSOP Pin Configuration
V
V
DD
SS
W
A
1
2
3
4
5
(Not to Scale)
AD5272/
Description
Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.
Terminal A of RDAC. V
Wiper terminal of RDAC. V
Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic capacitors
and 10 μF capacitors.
External Capacitor. Connect a 1 μF capacitor between EXT_CAP and V
rating of ≥7 V.
Ground Pin, Logic Ground Reference.
Hardware Reset Pin. Refreshes the RDAC register with the contents of the 50-TP memory register. Factory
default loads midscale until the first 50-TP wiper memory location is programmed. RESET is active low. Tie RESET
to V
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input registers. It is
a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input registers.
Tristate Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 11).
Leave floating or tie to V
AD5274
TOP VIEW
DD
if not used.
10
9
8
7
6
RESET
ADDR
SCL
SDA
GND
SS
≤ V
SS
.
SS
A
≤ V
≤ V
W
DD
≤ V
Rev. C | Page 10 of 28
.
DD
.
EXT_CAP
NOTES
1. THE EXPOSED PAD IS LEFT FLOATING
OR IS TIED TO V
V
V
DD
SS
W
Figure 5. LFCSP Pin Configuration
A
1
2
3
4
5
SS
. This capacitor must have a voltage
AD5272/
(EXPOSED
SS
AD5274
.
PAD)
10
9
8
7
6 GND
ADDR
SCL
SDA
RESET