EVAL-AD5290EBZ Analog Devices Inc, EVAL-AD5290EBZ Datasheet - Page 16

• Manufacturer Part Number: EVAL-AD5290EBZ
• Description: Eval Board For AD5290
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5290EBZ

• Main Purpose: Digital Potentiometer
• Utilized Ic / Part: AD5290
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5290
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider
at wiper to B and wiper to A proportional to the input voltage
at A to B. Unlike the polarity of V
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
If ignoring the effect of the wiper resistance for simplicity, con-
necting the A terminal to 30 V and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage
is equal to the voltage applied across Terminal A and Terminal B,
divided by the 256 positions of the potentiometer divider. The
general equation defining the output voltage at V
to ground for any valid input voltage applied to Terminal A and
Terminal B is
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
V
W
(
D
)
=
Figure 28. Potentiometer Mode Configuration
256
D
×
V
V
A
I
+
256
256
A
B
−
W
D
DD
WA
×
V
to GND, which must be
and R
B
V
O
WB
and not the
W
with respect
Rev. B | Page 16 of 20
(3)
3-WIRE SERIAL BUS DIGITAL INTERFACE
The AD5290 contains a 3-wire digital interface ( CS , CLK,
and SDI). The 8-bit serial word must be loaded MSB first.
The format of the word is shown in
sensitive CLK input requires clean transitions to avoid clocking
incorrect data into the serial input register. Standard logic fami-
lies work well. When
serial register on each positive clock edge.
The data setup and data hold times in the Specifications section
determine the valid timing requirements. The AD5290 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
Extra MSB bits are ignored.
DAISY CHAIN OPERATION
SDO shifts out the SDI content in the previous frame; thus it
can be used for daisy-chaining multiple devices. The SDO pin
contains an open drain N-Ch MOSFET and requires a pull-
up resistor if the SDO function is used. Users need to tie the
SDO pin of one package to the SDI pin of the next package.
Users may need to increase the clock period because the pull-up
resistor and the capacitive loading at the SDO to SDI interface
can induce time delay to the subsequent devices.
For example, in Figure 29, if two AD5290s are daisy-chained, a
total of 16 bits of data are required for each operation. The first
set of eight bits goes to U2, and the second set of eight bits goes
to U1. The CS should be kept low until all 16 bits are clocked
into their respective serial registers. The CS is then pulled high
to complete the operation.
SCLK
µC
MOSI
SS
SDI
Figure 29. Daisy Chain Configuration
CS
AD5290
CS is low, the clock loads data into the
U1
CLK
SDO
+5V
Table 4
R
2.2kΩ
PU
. The positive edge
SDI
CS
AD5290
U2
CLK
SDO