EVAL-AD5292EBZ Analog Devices Inc, EVAL-AD5292EBZ Datasheet - Page 8

• Manufacturer Part Number: EVAL-AD5292EBZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5292EBZ

• Main Purpose: Digital Potentiometer
• Embedded: Yes
• Utilized Ic / Part: AD5292
• Primary Attributes: 1 Channel, 256 Position
• Secondary Attributes: SPI Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5291/AD5292
Table 6.
Resistor
Tolerance per
Code
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
INTERFACE TIMING SPECIFICATIONS
V
Table 7.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
1
2
3
4
5
6
7
8
9
10
11 4
12 4
12 4
12 4
12 4
13 4
13 4
14 4
RESET
POWER-UP
All input signals are specified with t
Maximum SCLK frequency is 50 MHz.
Refer to t
R
Maximum time after V
DD
2
PULL_UP
4
/V
SS
= 2.2 kΩ to V
5
= ±15 V, V
12
and t
13
for RDAC register and memory commands operations.
LOGIC
LOGIC
LOGIC
Limit
20
10
10
10
5
5
1
400
14
1
40
2.4
410
8
1.5
450
1.3
450
20
2
R
From 0x08C
to 0x3FF
From 0X03C
to 0x3FF
From 0X028
to 0x3FF
, with a capacitance load of 168 pF.
|V
WB
is equal to 2.5 V.
3
DD
= 2.7 V to 5.5 V, −40°C < T
0
1
− V
SS
R
0
= t
| = 26 V to 33 V
F
= 1 ns/V (10% to 90% of V
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
μs max
ns max
ms max
ms min
ns max
ms max
ns max
ns min
ms max
R
From 0x000
to 0x35F
From 0x000
to 0x3C3
From 0x000
to 0x3D7
C3
WA
CONTROL BITS
C2
R
AB
C1
= 50 kΩ
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
RDY rising edge to SYNC falling edge
SYNC rising edge to RDY fall time
RDY low time, RDAC register write command execute time (R-Perf mode)
RDY low time, RDAC register write command execute time (normal mode)
RDY low time, memory program execute time
Software/hardware reset
RDY low time, RDAC register readback execute time
RDY low time, memory readback execute time
SCLK rising edge to SDO valid
Minimum RESET pulse width (asynchronous)
Power-on OTP restore time
R
From 0x0B4
to 0x3FF
From 0x050
to 0x3FF
From 0x032
to 0x3FF
A
|V
WB
C0
< +105°C. All specifications T
DD
DD
Figure 2. Shift Register Content
− V
DB9 (MSB)
) and timed from a voltage level of (V
D9
SS
Rev. D | Page 8 of 32
| = 21 V to 26 V
D8
R
From 0x000
to 0x31E
From 0x000
to 0x3AF
From 0x000
to 0x3CD
WA
D7
D6
DATA BITS
D5
R
From 0x04B
to 0x3FF
From 0x028
to 0x3FF
From 0x019
to 0x3FF
|V
WB
MIN
DD
to T
D4
− V
IL
+ V
SS
MAX
IH
| = 26 V to 33 V
D3
)/2.
, unless otherwise noted.
R
From 0x000
to 0x3B4
From 0x000
to 0x3D7
From 0x000
to 0x3E6
WA
D2
R
D1
AB
DB0 (LSB)
= 100 kΩ
D0
R
From 0x064
to 0x3FF
From 0x028
to 0x3FF
From 0x019
to 0x3FF
|V
WB
DD
− V
SS
| = 21 V to 26 V
R
From 0x000
to 0x39B
From 0x000
to 0x3D7
From 0x000
to 0x3E6
WA