EVAL-AD5522EBUZ Analog Devices Inc, EVAL-AD5522EBUZ Datasheet
EVAL-AD5522EBUZ
Specifications of EVAL-AD5522EBUZ
Related parts for EVAL-AD5522EBUZ
EVAL-AD5522EBUZ Summary of contents
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FEATURES Quad parametric measurement unit (PMU) FV, FI, FN (high-Z), MV, MI functions 4 programmable current ranges (internal R ±5 μA, ±20 μA, ±200 μA, and ± programmable current range up to ±80 mA (external R 22.5 V ...
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AD5522 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications..................................................................................... 6 Timing Characteristics .............................................................. 11 Absolute Maximum Ratings.......................................................... 15 Thermal Resistance .................................................................... 15 ESD Caution................................................................................ 15 Pin ...
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REVISION HISTORY 2/11—Rev Rev. D Changes to Measure Current, Gain Error Tempco Parameter....6 Changes to Force Current, Common Mode Error (Gain = 5) and Common Mode Error (Gain = 10) Parameters .....................7 Changes to Figure 5.........................................................................13 Changes to ...
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AD5522 GENERAL DESCRIPTION The AD5522 is a high performance, highly integrated parametric measurement unit consisting of four independent channels. Each per-pin parametric measurement unit (PPMU) channel includes five 16-bit, voltage output DACs that set the programmable input levels for the ...
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DVCC AVSS AVDD AGND VREF REG X2 REG 16 REFGND M REG × REG ×2 OFFSET DAC 16 16 ×6 16-BIT 16 X1 REG 16 FIN DAC M REG X2 REG C REG ×6 16 ...
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AD5522 SPECIFICATIONS AVDD ≥ AVSS ≤ −5 V; |AVDD − AVSS| ≥ and ≤ DVCC = 2 5.25 V; VREF = 5 V; REFGND = DUTGND = AGND = 0 V; gain ...
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Parameter Min 2 Measure Current Ranges 2 Noise Spectral Density (NSD) FORCE CURRENT 2 Voltage Compliance, FOHx AVSS + 4 2 Voltage Compliance, EXTFOHx AVSS + 3 Offset Error −0.5 2 Offset Error Tempco Gain Error −1.5 2 Gain Error ...
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AD5522 Parameter Min CURRENT CLAMPS Clamp Accuracy Programmed clamp value Programmed clamp value 2 CLL to CLH Recovery Time 2 Activation Time FOHx, EXTFOHx, EXTMEASILx, EXTMEASIHx, CFFx PINS 2 Pin Capacitance Leakage Current −3 2 Leakage Current ...
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Parameter Min GUARDx PIN Output Voltage Span Output Offset −10 Short-Circuit Current −15 2 Maximum Load Capacitance Output Impedance 2 Tristate Leakage Current −30 2 Slew Rate 2 Alarm Activation Time 2 FORCE AMPLIFIER Slew Rate Gain Bandwidth Max Stable ...
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AD5522 Parameter Min DIE TEMPERATURE SENSOR 2 Accuracy Output Voltage at 25°C 2 Output Scale Factor 2 Output Voltage Range 0 2 INTERACTION AND CROSSTALK DC Crosstalk (FOHx) DC Crosstalk (MEASOUTx) DC Crosstalk Within a Channel SPI INTERFACE LOGIC INPUTS ...
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Parameter Min 2 Power Supply Sensitivity ΔForced Voltage/ΔAVDD ΔForced Voltage/ΔAVSS ΔMeasured Current/ΔAVDD ΔMeasured Current/ΔAVSS ΔForced Current/ΔAVDD ΔForced Current/ΔAVSS ΔMeasured Voltage/ΔAVDD ΔMeasured Voltage/ΔAVSS ΔForced Voltage/ΔDVCC ΔMeasured Current/ΔDVCC ΔForced Current/ΔDVCC ΔMeasured Voltage/ΔDVCC 1 Typical specifications are at 25°C and nominal supply, ±15.25 ...
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AD5522 DVCC, Limit Parameter 2 2 1.8 1 670 700 17 t 400 400 Guaranteed by ...
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Circuit and Timing Diagrams DVCC R 2.2kΩ LOAD TO OUTPUT PIN 50pF C LOAD Figure 3. Load Circuit for CGALM , TMPALM SCLK SYNC t 7 DB28 SDI (N) BUSY 1 LOAD 1 FOHx 2 LOAD ...
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AD5522 SCLK SYNC DB28 SDI (N) SDO Figure 6. SPI Read Timing (Readback Word Contains 24 Bits and Can Be Clocked Out with a Minimum of 24 Clock Edges) SYNC SYNC t 3 SCLK SCLK MSB D28 SDI SDI SDO ...
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ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating Supply Voltage, AVDD to AVSS 34 V AVDD to AGND −0 +34 V AVSS to AGND +0 −34 V VREF to AGND −0 DUTGND to ...
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AD5522 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AVDD 1 CFF0 2 CCOMP0 3 EXTMEASIH0 4 EXTMEASIL0 5 FOH0 6 GUARD0 7 GUARDIN0/DUTGND0 8 MEASVH0 9 AGND 10 AGND 11 MEASVH2 12 GUARDIN2/DUTGND2 13 GUARD2 14 FOH2 15 EXTMEASIL2 16 EXTMEASIH2 17 ...
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Pin No. Mnemonic Description 13 GUARDIN2/ Guard Amplifier Input for Channel 2/DUTGND Input for Channel 2. This dual function pin is configured via the DUTGND2 serial interface. The default function at power-on is GUARDIN2. If this pin is configured as ...
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AD5522 Pin No. Mnemonic Description 49 MEASVH3 DUT Voltage Sense Input (High Sense) for Channel 3. 52 MEASVH1 DUT Voltage Sense Input (High Sense) for Channel 1. 53 GUARDIN1/ Guard Amplifier Input for Channel 1/DUTGND Input for Channel 1. This ...
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EXTFOH0 1 AVSS 2 RESET 3 TMPALM 4 CGALM 5 SPI/LVDS 6 AVDD 7 DUTGND 8 VREF 9 REFGND 10 SYS_SENSE 11 AGND 12 SYS_FORCE 13 AVSS 14 MEASOUT0 15 MEASOUT1 16 MEASOUT2 17 MEASOUT3 18 AVSS 19 EXTFOH1 20 ...
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AD5522 Pin No. Mnemonic Description 6 SPI/LVDS Interface Select Pin. Logic low selects SPI-compatible interface mode; logic high selects LVDS interface mode. This pin has a pull-down current source (~350 μA). In LVDS interface mode, the CPOHx and CPOLx pins ...
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Pin No. Mnemonic Description 46 CPOL2/CPO0 Comparator Output Low (Channel 2) for SPI Interface/Comparator Output Window (Channel 0) for LVDS Interface. 47 DVCC Digital Supply Voltage. 48 LOAD Logic Input (Active Low). This pin synchronizes updates within one device or ...
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AD5522 TYPICAL PERFORMANCE CHARACTERISTICS 1 25°C A 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 DNL –0.8 INL –1.0 0 10,000 20,000 30,000 40,000 CODE Figure 10. Force Voltage Linearity vs. Code, All Ranges, 1 LSB = 0.0015% ...
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AVDD = +15.5V, AVSS = –15.5V, 0.004 OFFSET DAC = 0xA492 AVDD = +28V, AVSS = –5V, OFFSET DAC = 0x0 0.003 AVDD = +10V, AVSS = –23V, OFFSET DAC = 0xED87 0.002 0.001 0 –0.001 –0.002 –0.003 0 ...
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AD5522 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 10 100 1k 10k FREQUENCY (Hz) Figure 22. ACPSRR at FOHx in Force Current Mode vs. Frequency (MI Gain = 10) 0 –10 –20 –30 –40 –50 –60 ...
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FREQUENCY (Hz) Figure 28. APCSRR at MEASOUTx in Measure Current Mode vs. Frequency (MI Gain = 10, MEASOUT Gain = 0.2) 0 –10 ...
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AD5522 T = 25° FOHx VICTIM 2 MEASOUTx VICTIM MEASOUTx 3 ATTACK TRIGGER CH1 10.0mV CH2 50.0mV W W CH3 5.00V CH4 5.00V CH2 Pk-Pk 14.38mV Figure 34. Shorted DUT AC Crosstalk, Victim PMU in ...
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SYNC 4 BUSY 3 FOH0 CH1 100.0mV CH3 5.00V M2.00µ 6.00000µs B CH4 5.00V W Figure 40. Range Change, PMU0, ±20 μA to ±2 mA 150 kΩ ...
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AD5522 SYNC 4 BUSY 3 MEASOUTx (MI) 2 FOHx 1 CH1 2.00V CH2 10.0V M10.0µs CH3 5.00V CH4 5.00V Figure 46. FV Settling ±200 μA Range, C CCOMPx = 100 pF, R LOAD CH1 3.20V ...
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TERMINOLOGY Offset Error Offset error is a measure of the difference between the actual voltage and the ideal voltage at midscale or at zero current expressed FSR. Gain Error Gain error is the difference between full-scale ...
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AD5522 THEORY OF OPERATION The AD5522 is a highly integrated, quad per-pin parametric measurement unit (PPMU) for use in semiconductor automated test equipment. It provides programmable modes to force a pin voltage and measure the corresponding current (FVMI) and to ...
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When the AD5522 is placed in high-Z mode, the clamp circuit is always configured to monitor the measure current signal (irrespective of which high-Z mode is selected, high high-Z I). At this time, the clamp circuit is also ...
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AD5522 MEASURE CURRENT GAINS The measure current amplifier has two gain settings, 5 and 10. The two gain settings allow users to achieve the quoted/specified current ranges with large or small voltage swing. Use the 10 gain setting with a ...
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CHOOSING POWER SUPPLY RAILS As noted in the Specifications section, the minimum supply variation across the part |AVDD − AVSS| ≥ For the AD5522 circuits to operate correctly, the supply rails must take into account not only the ...
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AD5522 When configured as DUTGND per channel, this dual function pin is no longer connected to the input of the guard amplifier. Instead connected to the low end of the instrumentation amplifier (SW14a), and the input of the ...
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SYSTEM FORCE AND SENSE SWITCHES Each channel has switches to allow connection of the force (FOHx) and sense (MEASVHx) lines to a central PMU for calibration purposes. There is one set of SYS_FORCE and SYS_SENSE pins per device ...
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AD5522 DAC LEVELS Each channel contains five dedicated DAC levels: one for the force amplifier, one each for the clamp high and clamp low levels, and one each for the comparator high and comparator low levels. The architecture of a ...
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The calibration engine is engaged only when data is written to the X1 register and for some PMU writes (see Table 18). The calibration engine is not engaged when data is written to the register. This has ...
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AD5522 Table 14. References Suggested For Use with AD5522 Initial Part No. Voltage (V) Accuracy % ADR435 5 ±0.04 ADR445 5 ±0.04 ADR431 2.5 ±0.04 ADR441 2.5 ±0.04 1 Subset of the possible references suitable for use with the AD5522. ...
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Calibration Example Nominal offset coefficient = 32,768 Nominal gain coefficient = 65,535 For example, the gain error = 0.5%, and the offset error = 100 mV. Gain error (0.5%) calibration: 65,535 × 0.995 = 65,207 Therefore, load Code 1111 1110 ...
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AD5522 CIRCUIT OPERATION FORCE VOLTAGE (FV) MODE Most PMU measurements are performed in force voltage/measure current (FVMI) mode, for example, when the device is used as a device power supply continuity or leakage testing. In force voltage (FV) ...
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FORCE CURRENT (FI) MODE In force current (FI) mode, the voltage at the FIN DAC is converted to a current and is applied to the DUT. The feedback path is the measure current amplifier, feeding back the voltage measured across ...
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AD5522 SERIAL INTERFACE The AD5522 provides two high speed serial interfaces: an SPI- compatible interface operating at clock frequencies MHz and an EIA-644-compliant LVDS interface. To minimize both the power consumption of the device and the on-chip ...
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Because there is only one calibration engine shared among four channels, the task of calculating X2 values must be done sequentially, so that the length of the BUSY pulse varies according to the number of channels being updated. Following any ...
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AD5522 REGISTER UPDATE RATES The value of the X2 register is calculated each time the user writes new data to the corresponding X1 register and for some PMU register updates. The calculation is performed in a three-stage process. The first ...
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All codes not explicitly referenced in this table are reserved and should not be used (see Table 29). Table 20. Read and Write Functions of the AD5522 B28 B27 B26 B25 B24 RD/WR PMU3 PMU2 PMU1 PMU0 Write Functions 0 ...
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AD5522 WRITE SYSTEM CONTROL REGISTER The system control register is accessed when the PMU channel address bits (PMU3 to PMU0) and the mode bits (MODE1 and MODE0) are all 0s. This register allows quick setup of various Table 21. System ...
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Bit Bit Name Description 7 GAIN1 MEASOUTx output range. The MEASOUTx range defaults to the force voltage span for voltage and current measurements, which includes some overrange to allow for offset correction. The nominal output voltage range is 6 GAIN0 ...
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AD5522 WRITE PMU REGISTER To address PMU functions, set the MODE1 and MODE0 bits to 0. This setting selects the PMU register (see Table 19 and Table 20). The AD5522 has very flexible addressing, which allows writing of data to ...
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Bit Bit Name Description 14 MEAS1 The MEAS1 and MEAS0 bits specify the required measure mode, allowing the MEASOUTx line to be disabled, connected to the temperature sensor, or enabled for measurement of current or voltage. 13 MEAS0 MEAS1 0 ...
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AD5522 WRITE DAC REGISTER The DAC input, gain, and offset registers are addressed through a combination of PMU bits (Bit 27 to Bit 24) and mode bits (Bit 23 and Bit 22). Bit A5 to Bit A0 address each DAC ...
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DAC Addressing For the FIN and comparator (CPH and CPL) DACs, there is a set of X1, M, and C registers for each current range, and one set for the voltage range; for the clamp DACs (CLL and CLH), there ...
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AD5522 ...
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READ REGISTERS Readback of all the registers in the device is possible via the SPI and the LVDS interfaces. To read data from a register first necessary to write a readback command to tell the device which register ...
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AD5522 READBACK OF SYSTEM CONTROL REGISTER The system control register readback function is a 24-bit word. Mode and system control register data bits are shown in Table 31. Table 31. System Control Register Readback Bit Bit Name Description 23 (MSB) ...
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READBACK OF PMU REGISTER The PMU register readback function is a 24-bit word that includes the mode and PMU data bits. Only one PMU register can be read back at any one time. Table 32. PMU Register Readback Bit Bit ...
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AD5522 READBACK OF COMPARATOR STATUS REGISTER The comparator status register is a read-only register that provides access to the output status of each comparator pin on the chip. Table 33 shows the format of the comparator register readback word. Table ...
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READBACK OF DAC REGISTER The DAC register readback function is a 24-bit word that includes the mode, address, and DAC data bits. Table 35. DAC Register Readback Bit Bit Name 23 (MSB) MODE1 22 MODE0 DAC Register-Specific Bits 21 to ...
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AD5522 APPLICATIONS INFORMATION POWER-ON DEFAULT The power-on default for all DAC channels is that the contents of each M register are set to full scale (0xFFFF), and the contents of each C register are set to midscale (0x8000). The contents ...
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CHANGING MODES There are different ways of handling a mode change. 1. Load any DAC X1 values that require changes. Remember that for force amplifier and comparator DACs, X1 registers are available per voltage and current range, so the user ...
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AD5522 Table 39. ADCs and ADC Drivers Suggested For Use with AD5522 Sample Part No. Resolution Rate Ch. No. AD7685 16 250 kSPS 1 AD7686 16 500 kSPS 1 3 AD7693 16 500 kSPS 1 AD7610 16 250 kSPS 1 ...
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DAC CENTRAL GUARD AMP PMU ADC VCH DAC V TERM DAC TIMING DATA MEMORY VH DAC TIMING FORMATTER GENERATOR DRIVER DESKEW DLL, LOGIC VL DAC VCL DAC DAC VTH COMPARE FORMATTER COMP MEMORY DESKEW VTL DAC ACTIVE LOAD IOL DAC ...
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AD5522 OUTLINE DIMENSIONS 0.75 0.60 0.45 0° MIN 1.05 0.20 1.00 0.09 0.95 7° 3.5° 0.15 0° SEATING 0.05 0.08 MAX PLANE COPLANARITY VIEW A ROTATED 90 ° CCW 0.75 0.60 0.45 0° MIN 1.05 0.20 1.00 0.09 0.95 7° ...
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... ORDERING GUIDE 1 Model Temperature Range (T AD5522JSVDZ 25°C to 90°C AD5522JSVUZ 25°C to 90°C EVAL-AD5522EBDZ EVAL-AD5522EBUZ RoHS Compliant Part. ) Package Description J 80-Lead TQFP_EP with Exposed Pad on Bottom 80-Lead TQFP_EP with Exposed Pad on Top Evaluation Board with Exposed Pad on Bottom Evaluation Board with Exposed Pad on Top Rev ...
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AD5522 NOTES ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06197-0-2/11(D) Rev Page ...