EVAL-AD7401EDZ Analog Devices Inc, EVAL-AD7401EDZ Datasheet - Page 4

• Manufacturer Part Number: EVAL-AD7401EDZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc
• Series: iCoupler®r

Specifications of EVAL-AD7401EDZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 20M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±320 mV
• Power (typ) @ Conditions: 100mW @ 20MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: AD7401
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7401
Parameter
LOGIC OUTPUTS
POWER REQUIREMENTS
1
2
3
4
5
6
7
TIMING SPECIFICATIONS
V
Table 2.
Parameter
f
t
t
t
t
1
2
3
4
MCLKIN
1
2
3
4
Temperature range is −40°C to +85°C.
All voltages are relative to their respective ground.
See the
For f
Sample tested during initial release to ensure compliance.
See
See
Sample tested during initial release to ensure compliance
Mark space ratio for clock input is 40/60 to 60/40 for f
V
Measured with the load circuit of
4
DD1
4
DD1
Output High Voltage, V
Output Low Voltage, V
V
V
I
I
DD1
DD2
DD1
DD2
Figure 15
Figure 17
MCLK
= V
= 4.5 V to 5.25 V, V
2, 3
6
7
DD2
Terminology
> 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, V
= 5 V
.
.
±
5% for f
section.
Limit at T
20
5
25
15
0.4 × t
0.4 × t
MCLKIN
OL
DD2
OH
MCLKIN
MCLKIN
> 16 MHz to 20 MHz.
= 3 V to 5.5 V, T
Figure 2
MIN
MCLKIN
, T
MDAT
MAX
and defined as the time required for the output to cross 0.8 V or 2.0 V.
Figure 2. Load Circuit for Digital Output Timing Specifications
A
MCLKIN
= T
Y Version
V
0.4
4.5/5.25
3/5.5
12
8
4
DD2
Unit
MHz max
MHz min
ns max
ns min
ns min
ns min
to 16 MHz and 48/52 to 52/48 for f
TO OUTPUT
MAX
− 0.1
to T
DD1
PIN
1, 2
MIN
= V
t
25pF
1
Figure 3. Data Timing
DD2
, unless otherwise noted.
Rev. C | Page 4 of 20
C
Unit
V min
V max
V min/V max
V min/V max
mA max
mA max
mA max
L
= 5 V ± 5%, and T
200µA
200µA
I
I
t
OL
OH
2
A
MCLKIN
= −40°C to +85°C.
Description
Master clock input frequency
Master clock input frequency
Data access time after MCLK rising edge
Data hold time after MCLK rising edge
Master clock low time
Master clock high time
> 16 MHz to 20 MHz.
Test Conditions/Comments
I
I
V
V
V
1.6V
O
O
DD1
DD2
DD2
t
= −200 μA
= +200 μA
3
1
= 5.25 V
= 5.5 V
= 3.3 V
t
4