EVAL-AD9834SDZ Analog Devices Inc, EVAL-AD9834SDZ Datasheet

no-image

EVAL-AD9834SDZ

Manufacturer Part Number
EVAL-AD9834SDZ
Description
Evaluation Board I.c.
Manufacturer
Analog Devices Inc
Datasheet

Specifications of EVAL-AD9834SDZ

Lead Free Status / Rohs Status
Lead free / RoHS Compliant
FEATURES
Narrow-band SFDR >72 dB
2.3 V to 5.5 V power supply
Output frequency up to 37.5 MHz
Sine output/triangular output
On-board comparator
3-wire SPI® interface
Extended temperature range: −40°C to +105°C
Power-down option
20 mW power consumption at 3 V
20-lead TSSOP
APPLICATIONS
Frequency stimulus/waveform generation
Frequency phase tuning and modulation
Low power RF/communications systems
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect
Test and medical equipment
GENERAL DESCRIPTION
The AD9834 is a 75 MHz low power DDS device capable of
producing high performance sine and triangular outputs. It also
has an on-board comparator that allows a square wave to be
produced for clock generation. Consuming only 20 mW of power
at 3 V makes the AD9834 an ideal candidate for power-sensitive
applications.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
detection
FSELECT
MCLK
28-BIT FREQ0
28-BIT FREQ1
FSYNC
AVDD
REG
REG
SERIAL INTERFACE
CONTROL LOGIC
SCLK
AGND
AND
MUX
12-BIT PHASE0 REG
12-BIT PHASE1 REG
SDATA
DGND
16-BIT CONTROL
REGISTER
ACCUMULATOR
FUNCTIONAL BLOCK DIAGRAM
(28-BIT)
PHASE
REGULATOR
DVDD
PSELECT
CAP/2.5V
MUX
Σ
12
Figure 1.
VCC
2.5V
MUX
MUX
ROM
SLEEP RESET
SIN
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Capability for phase modulation and frequency modulation is
provided. The frequency registers are 28 bits; with a 75 MHz clock
rate, resolution of 0.28 Hz can be achieved. Similarly, with a 1 MHz
clock rate, the AD9834 can be tuned to 0.004 Hz resolution.
Frequency and phase modulation are affected by loading registers
through the serial interface and toggling the registers using
software or the FSELECT pin and PSELECT pin, respectively.
The AD9834 is written to using a 3-wire serial interface. This
serial interface operates at clock rates up to 40 MHz and is
compatible with DSP and microcontroller standards.
The device operates with a power supply from 2.3 V to 5.5 V.
The analog and digital sections are independent and can be run
from different power supplies, for example, AVDD can equal
5 V with DVDD equal to 3 V.
The AD9834 has a power-down pin (SLEEP) that allows
external control of the power-down mode. Sections of the
device that are not being used can be powered down to
minimize the current consumption. For example, the DAC can
be powered down when a clock output is being generated.
The part is available in a 20-lead TSSOP.
REFERENCE
ON-BOARD
DIVIDED
BY 2
20 mW Power, 2.3 V to 5.5 V,
MUX
MSB
REFOUT
75 MHz Complete DDS
FULL-SCALE
COMPARATOR
©2003–2011 Analog Devices, Inc. All rights reserved.
CONTROL
10-BIT
DAC
FS ADJUST
AD9834
COMP
IOUT
IOUTB
SIGN BIT OUT
VIN
AD9834
www.analog.com

Related parts for EVAL-AD9834SDZ

EVAL-AD9834SDZ Summary of contents

Page 1

FEATURES Narrow-band SFDR > 5.5 V power supply Output frequency up to 37.5 MHz Sine output/triangular output On-board comparator 3-wire SPI® interface Extended temperature range: −40°C to +105°C Power-down option 20 mW power consumption at 3 ...

Page 2

... Grounding and Layout .................................................................. 26 Interfacing to Microprocessors..................................................... 27 AD9834 to ADSP-21xx Interface ............................................. 27 AD9834 to 68HC11/68L11 Interface....................................... 27 AD9834 to 80C51/80L51 Interface .......................................... 28 AD9834 to DSP56002 Interface ............................................... 28 Evaluation Board ............................................................................ 29 System Development Platform................................................. 29 AD9834 to SPORT Interface..................................................... 29 XO vs. External Clock................................................................ 29 Power Supply............................................................................... 29 Evaluation Board Schematics ................................................... 30 Evaluation Board Layout........................................................... 32 Outline Dimensions ....................................................................... 35 Ordering Guide .......................................................................... 35 Rev Page ...

Page 3

... Section ..............................................................................................29 Deleted Bill of Materials, Table 19; Renumbered Sequentially ..............................................................30 Added Evaluation Board Schematics Section and Figure 41 ....30 Added Figure 42 ..............................................................................31 Added Evaluation Board Layout Section and Figure 43 ............32 Added Figure 44 ..............................................................................33 Added Figure 45 ..............................................................................34 Changes to Ordering Guide...........................................................35 4/10—Rev Rev. B Changes to Comparator Section ...................................................15 Added Figure 28 ...

Page 4

SPECIFICATIONS VDD = 2 5.5 V, AGND = DGND = Table 1. Parameter 2 SIGNAL DAC SPECIFICATIONS Resolution Update Rate 3 I Full Scale OUT V Max OUT V Min OUT 4 Output Compliance DC ...

Page 5

Parameter POWER SUPPLIES AVDD DVDD Grade C Grade Grade C Grade Low Power Sleep Mode B Grade C Grade 1 B grade: MCLK = 50 ...

Page 6

AD9834 TIMING CHARACTERISTICS DVDD = 2 5.5 V, AGND = DGND = 0 V, unless otherwise noted. Table 2. 1 Parameter Limit MIN MAX t 20/13 ...

Page 7

ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter AVDD to AGND DVDD to DGND AVDD to DVDD AGND to DGND CAP/2.5V Digital I/O Voltage to DGND Analog I/O Voltage to AGND Operating Temperature Range Industrial ...

Page 8

AD9834 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin No. Mnemonic Description ANALOG SIGNAL AND REFERENCE 1 FS ADJUST Full-Scale Adjust Control. A resistor (R of the full-scale DAC current. The relationship between R IOUT FULL SCALE ...

Page 9

Pin No. Mnemonic Description 13 SDATA Serial Data Input. The 16-bit serial data-word is applied to this input. 14 SCLK Serial Clock Input. Data is clocked into the AD9834 on each falling SCLK edge. 15 FSYNC Active Low Control Input. ...

Page 10

AD9834 TYPICAL PERFORMANCE CHARACTERISTICS 4 25°C A 3.5 3.0 2.5 5V 2.0 1.5 1.0 0 MCLK FREQUENCY (MHz) Figure 7. Typical Current Consumption (I 4 25°C A 3.5 3.0 2.5 2.0 ...

Page 11

TEMPERATURE (°C) Figure 13. Wake-Up Time vs. Temperature 1.250 1.225 UPPER RANGE 1.200 1.175 LOWER RANGE 1.150 1.125 1.100 –40 25 TEMPERATURE (°C) Figure 14. ...

Page 12

AD9834 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 RWB 1k VWB 300 FREQUENCY (Hz) Figure 19 MHz 1.43 MHz = f MCLK OUT Frequency Word = 2492492 0 –10 –20 ...

Page 13

RWB 1k VWB 300 FREQUENCY (Hz) Figure 25 MHz 7.143 MHz = f MCLK OUT Frequency Word = 2492492 0 –10 –20 –30 ...

Page 14

AD9834 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 LSB below the ...

Page 15

THEORY OF OPERATION Sine waves are typically thought of in terms of their magnitude form a(t) = sin (ωt). However, these are nonlinear and not easy to generate except through piecewise construction. On the other hand, the angular information is ...

Page 16

AD9834 CIRCUIT DESCRIPTION The AD9834 is a fully integrated direct digital synthesis (DDS) chip. The chip requires one reference clock, one low precision resistor, and eight decoupling capacitors to provide digitally created sine waves up to 37.5 MHz. In addition ...

Page 17

The AD9834 is a sampled signal with its output following Nyquist sampling theorem. Specifically, its output spectrum contains the fundamental plus aliased signals (images) that occur at multiples of the reference clock frequency and the selected output frequency. A graphical ...

Page 18

AD9834 FUNCTIONAL DESCRIPTION SERIAL INTERFACE The AD9834 has a standard 3-wire serial interface that is com- patible with SPI, QSPI™, MICROWIRE™, and DSP interface standards. Data is loaded into the device as a 16-bit word under the control of a ...

Page 19

SLEEP12 SLEEP1 PHASE ACCUMULATOR (28-BIT) MODE + OPBITEN SIGN/PIB OPBITEN DB15 DB14 DB13 DB12 DB11 0 0 B28 HLB FSEL Table 6. Description of Bits in the Control Register Bit Name Description DB13 B28 Two write operations are required to ...

Page 20

AD9834 Bit Name Description DB5 OPBITEN The function of this bit is to control whether there is an output at the SIGN BIT OUT pin. This bit should remain the user is not using the SIGN BIT ...

Page 21

WRITING TO A FREQUENCY REGISTER When writing to a frequency register, Bit DB15 and Bit DB14 give the address of the frequency register. Table 10. Frequency Register Bits DB15 DB14 DB13 . . . DB0 FREQ0 REG ...

Page 22

AD9834 Table 16. Applying the SLEEP Function SLEEP SLEEP1 SLEEP12 PIN/SW Pin Bit Bit Bit DAC ...

Page 23

APPLICATIONS INFORMATION Because of the various output options available from the part, the AD9834 can be configured to suit a wide variety of applications. One of the areas where the AD9834 is suitable is in modulation applications. The part can ...

Page 24

AD9834 USING CONTROL BIT (CONTROL REGISTER WRITE) USING CONTROL BIT (CONTROL REGISTER WRITE) RESET BIT = 0 FSEL = SELECTED FREQUENCY REGISTER PSEL = SELECTED PHASE REGISTER PIN/ DATA WRITE WRITE A FULL 28-BIT WORD TO A FREQUENCY ...

Page 25

SELECT DATA SOURCES YES SET FSELECT FSELECT AND PSELECT AND PSELECT PINS BEING USED? NO (CONTROL REGISTER WRITE) PIN/ (CONTROL REGISTER WRITE) SET FSEL BIT SET PSEL BIT Figure 34. Selecting Data Sources Rev Page 25 ...

Page 26

AD9834 GROUNDING AND LAYOUT The printed circuit board (PCB) that houses the AD9834 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes ...

Page 27

INTERFACING TO MICROPROCESSORS The AD9834 has a standard serial interface that allows the part to interface directly with several microprocessors. The device uses an external serial clock to write the data/control information into the device. The serial clock can have ...

Page 28

AD9834 AD9834 TO 80C51/80L51 INTERFACE Figure 37 shows the serial interface between the AD9834 and the 80C51/80L51 microcontroller. The microcontroller is operated in Mode 0 so that TXD of the 80C51/80L51 drives SCLK of the AD9834, and RXD drives the ...

Page 29

... The system development platform (SDP hardware and software evaluation tool for use in conjunction with product evaluation boards. The SDP board is based on the Black fin ® BF527 processor with USB connectivity to the PC through a USB 2.0 high speed port. For more information about this device, go to: www ...

Page 30

... AD9834 EVALUATION BOARD SCHEMATICS Figure 41. AD9834 Evaluation Board Schematic, Part A Rev Page 02705-043 ...

Page 31

... Figure 42. AD9834 Evaluation Board Schematic, Part B—J1 Header Connector Rev Page AD9834 02705-044 ...

Page 32

... AD9834 EVALUATION BOARD LAYOUT Figure 43. AD9834 Evaluation Board Component Side Rev Page ...

Page 33

... Figure 44. AD9834 Evaluation Board Silkscreen Rev Page AD9834 ...

Page 34

... AD9834 Figure 45. AD9834 Evaluation Board Solder Side Rev Page ...

Page 35

... Maximum MCLK (MHz) AD9834BRU 50 AD9834BRU-REEL 50 AD9834BRU-REEL7 50 AD9834BRUZ 50 AD9834BRUZ-REEL 50 AD9834BRUZ-REEL7 50 AD9834CRUZ 75 AD9834CRUZ-REEL7 75 EVAL-AD9834SDZ RoHS Compliant Part. 2 For the EVAL-AD9834SDZ, a SDP board is required. 6.60 6.50 6. 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.20 0.05 0.09 0.30 0.19 SEATING ...

Page 36

AD9834 NOTES ©2003–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02705-0-2/11(C) Rev Page ...

Related keywords