KSZ8842-PMBL Micrel Inc, KSZ8842-PMBL Datasheet
KSZ8842-PMBL
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KSZ8842-PMBL Summary of contents
Page 1
... The KSZ8842-series of 2-port switches includes PCI and non-PCI CPU interfaces. This datasheet describes the KSZ8842-PMQL/PMBL PCI KSZ8842-PMQL is PQFP package chip, KSZ8842-PMBL is LFBGA package chip. For information on the KSZ8842-MQL/MBL CPU non-PCI interface switches, refer to the KSZ8842-MQL/MBL datasheet. The KSZ8842-PMQL/PMBL is the industry’s first fully managed 2-port switch with a 32 bit/33MHz PCI processor interface ...
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... The PCI configuration registers are used to initialize and configure the PCI interface • The PCI control/status registers are used to communicate between the host and KSZ8842- PMQL/PMBL • Switch registers are used to support transceiver control and status. They are configurable on-the-fly (port- priority, 802 ...
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... Add the base address and range for host MIB, change description for soft reset and other. 1.4 06/01/07 Add the package thermal information in the operating ratings. 1.5 10/02/07 Add the KSZ8842-PMBL BGA device information. October 2007 Operation Package Temp. Range o o ...
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... Micrel, Inc. Contents Pin Configuration .............................................................................................................................................................. 9 Pins Description of KSZ8842-PMQL.............................................................................................................................. 11 Functional Description ................................................................................................................................................... 20 Functional Overview: PCI Bus Interface Unit............................................................................................................... 20 PCI Bus Interface.......................................................................................................................................................... 20 TXDMA Logic and TX Buffer Manager ......................................................................................................................... 20 RXDMA Logic and RX Buffer Manager ........................................................................................................................ 20 Functional Overview: Physical Layer Transceiver (PHY) ........................................................................................... 20 100BASE-TX Transmit.................................................................................................................................................. 20 100BASE-TX Receive................................................................................................................................................... 20 PLL Clock Synthesizer (Recovery) ............................................................................................................................... 21 Scrambler/De-scrambler (100BASE-TX Only) ...
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... MAC Address Register 1 (Offset 0x0470): MACAR1 ................................................................................................... 58 MAC Address Register 2 (Offset 0x0472): MACAR2 ................................................................................................... 58 MAC Address Register 3 (Offset 0x0474): MACAR3 ................................................................................................... 58 Reserved (Offset 0x0476 - 0x047F) ............................................................................................................................. 58 Priority Control Register 1 (Offset 0x0480): TOSR1..................................................................................................... 59 TOS Priority Control Register 2 (Offset 0x482): TOSR2 .............................................................................................. 59 TOS Priority Control Register 3 (Offset 0x484): TOSR3 .............................................................................................. 60 October 2007 5 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... Port 2 Reserved (Offset 0x0536 – 0x053A).................................................................................................................. 95 Host Control Register 1 (Offset 0x0540): P3CR1 ......................................................................................................... 95 Host Control Register 2 (Offset 0x0542): P3CR2 ......................................................................................................... 96 Host VID Control Register (Offset 0x0544): P3VIDCR................................................................................................. 97 Host Control Register 3 (Offset 0x0546): P3CR3 ......................................................................................................... 97 Host Ingress Rate Control Register (Offset 0x0548): P3IRCR..................................................................................... 98 October 2007 6 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... Absolute Maximum Ratings ...................................................................................................................................... 109 (2) Operating Ratings ...................................................................................................................................................... 109 (4) Electrical Characteristics .......................................................................................................................................... 109 Timing Diagrams ........................................................................................................................................................... 111 EEPROM Timing......................................................................................................................................................... 111 Auto Negotiation Timing.............................................................................................................................................. 112 Reset Timing............................................................................................................................................................... 113 Selection of Isolation Transformers............................................................................................................................ 114 Selection of Reference Crystal .................................................................................................................................... 114 Package Information ..................................................................................................................................................... 115 Acronyms and Glossary............................................................................................................................................... 117 October 2007 7 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... Micrel, Inc. List of Figures Figure 1. KSZ8842-PMQL/PMBL Functional Diagram ....................................................................................................... 1 Figure 2. KSZ8842-PMQL 128-Pin PQFP (Top View)........................................................................................................ 9 Figure 3. KSZ8842-PMBL 100-Ball LFBGA (Top View) .................................................................................................. 10 Figure 4. Typical Straight Cable Connection ................................................................................................................... 22 Figure 5. Typical Crossover Cable Connection ............................................................................................................... 23 Figure 6. Auto Negotiation and Parallel Operation .......................................................................................................... 24 Figure 7. Destination Address Lookup Flow Chart, Stage 1 ............................................................................................ 26 Figure 8 ...
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... Micrel, Inc. Pin Configuration October 2007 Figure 2. KSZ8842-PMQL 128-Pin PQFP (Top View) 9 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... Micrel, Inc. Balls Configuration October 2007 Figure 3. KSZ8842-PMBL 100-Ball LFBGA (Top View) 10 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... Micrel, Inc. Pins Description of KSZ8842-PMQL Pin Pin Type Number Name 1 TEST_EN I 2 SCAN_EN I 3 P1LED2 Opu 4 P1LED1 Opu 5 P1LED0 Opu 6 P2LED2 Opu 7 P2LED1 Opu 8 P2LED0 Opu 9 DGND Gnd 10 VDDIO P October 2007 Pin Function Test Enable For normal operation, pull-down this pin to ground. ...
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... EEPROM. EEPROM Data In This pin is connected to DO output of the serial EEPROM. No connect 3.3V digital I 3.3V digital I Digital ground Digital ground Full-chip power-down input. Active Low. Analog ground 1.2V analog V DD Analog ground No connect 12 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... X2 is not connected. Note: Clock is ±50ppm for both crystal and oscillator. Hardware Reset, Active Low RSTN will cause the KSZ8842-PMQL to reset all of its functional blocks. RSTN must be asserted for a minimum duration of 10 ms. PCI Parity Even parity computed for PAD [31:0] and CBE [3:0]N, master drives PAR for address and write data phase, target drives PAR for read data phase ...
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... This signal is asserted low to indicate to the KSZ8842-PMQL that it has been granted the PCI bus master operation. PCI Parity Error The KSZ8842-PMQL as a master or target will assert this signal low to indicate a parity error on any incoming data bus master, it will monitor this signal on all write operations. ...
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... PCI Address / Data 8 PCI Address / Data 7 PCI Address / Data 6 PCI Address / Data 5 PCI Address / Data 4 PCI Address / Data 3 Digital I/O ground Digital core ground 3.3V digital I PCI Address / Data 2 PCI Address / Data 1 PCI Address / Data 0 Table 1. KSZ8842-PMQL Pin Description 15 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... Micrel, Inc. Balls Description of KSZ8842-PMBL Ball Ball Type Number Name A8 TEST_EN I C7 SCAN_EN I B7 P1LED2 Opu A7 P1LED1 Opu C6 P1LED0 Opu B6 P2LED2 Opu A6 P2LED1 Opu B5 P2LED0 Opu A5 PCLK Ipd October 2007 Ball Function Test Enable. For normal operation, pull-down this pin to ground. ...
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... connect. Note: Clock is ± 50ppm for both crystal and oscillator. Hardware Reset, Active Low RSTN will cause the KSZ8842-PMBL to reset all of its functional blocks. RSTN must be asserted for a minimum duration of 10 ms. PCI Parity Even parity computed for PAD [31:0] and CBE[3:0]N, master drives PAR for address and write data phase, target drives PAR for read data phase ...
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... This signal is asserted low to indicate to the KSZ8842-PMBL that it has been granted the PCI bus master operation. PCI Parity Error The KSZ8842-PMBL as a master or target will assert this signal low to indicate a parity error on any incoming data bus master, it will monitor this signal on all write operations. PCI System Error This system error signal is asserted low by the KSZ8842-PMBL ...
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... This ball is used to provide 1.2V power supply to all 1.2V power VDDC and VDDA recommended the ball should be connected to 3.3V power rail by a 100ohm resistor for the internal LDO application. 1.2V analog V DD 3.3V digital I 3.3V analog V DD 3.3V analog V DD Ground Table 2. KSZ8842-PMBL Ball Description 19 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... TX buffer. The KSZ8842-PMQL/PMBL uses 4K bytes of transmit data buffer between the TXDMA logic and transmit MAC. When the TXDMA logic determines there is enough space available in the TX buffer, the TXDMA logic will move any pending frame data into the TX buffer ...
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... RXP-or-RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8842-PMQL/PMBL decodes a data frame. The receiver clock is maintained active during idle periods in between data reception. ...
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... October 2007 MDI MDI-X RJ45 RJ45 Signals Pins Pins RD- 6 Table 3. MDI/MDI-X Pin Definitions Figure 4. Typical Straight Cable Connection 22 KSZ8842-PMQL/PMBL Signals RD+ RD- TD+ TD- M9999-100207-1.5 ...
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... If auto negotiation is not supported or the link partner to the KSZ8842-PMQL/PMBL is forced to bypass auto negotiation, the mode is set by observing the signal at the receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listening for advertisements or a fixed signal protocol ...
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... Set Link Mode LinkMD Cable Diagnostics The KSZ8842-PMQL/PMBL LinkMD uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with a maximum distance of 200m and an accuracy of ± ...
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... IIf P1VCT[14-13]=11 or P2VCT[14-13]=11, this indicates an invalid test, and occurs when the KSZ8842-PMQL/PMBL is unable to shut down the link partner. In this instance, the test is not run not possible for the KSZ8842- PMQL/PMBL to determine if the detected signal is a reflection of the signal generated or a signal from another source. ...
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... Micrel, Inc. Forwarding The KSZ8842-PMQL/PMBL forwards packets using the algorithm that is depicted in the following flowcharts. Figure 7 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “ ...
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... Switching Engine The KSZ8842-PMQL/PMBL features a high-performance switching engine to move data to and from the MAC’s packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The switching engine has a 32KB internal frame buffer. This resource is shared between all the ports. There are a total of 256 buffers available ...
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... The flow control is based on availability of the system resources, including available buffers, available transmit queues, and available receive queues. The KSZ8842-PMQL/PMBL will flow control a port that has just received a packet if the destination port resource is busy. The KSZ8842-PMQL/PMBL issues a flow control frame (XON), containing the maximum pause time defined in IEEE standard 802 ...
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... Repeater Mode When KSZ8842-PMQL/PMBL is set to repeater mode (SGCR3[7] = 1), it only works on 100BT half-duplex mode. In repeater enabled mode, all ingress packets will broadcast to other two ports without MAC check and learning. Before setting the device to repeater mode, the user has to set bit 13 (100Mbps), bit 12 (auto-negotiation disabled) and bit 8 (half duplex) in both P1MBCR and P2MBCR registers as well as to set bit 6 (host half duplex) in SGCR3 register for repeater mode ...
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... A packet received on port 1 is destined to port 2 after the internal lookup. The KSZ8842-PMQL/PMBL forwards the packet to both port 2 and the host port. The KSZ8842- PMQL/PMBL can optionally even forward “bad” received packets to the “sniffer port”. ...
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... A packet received on port 1 is destined to port 2 after the internal lookup. The KSZ8842-PMQL/PMBL forwards the packet to both port 2 and the host port. Multiple ports can be selected as “receive sniff” or “transmit sniff”. In addition, any port can be selected as the “sniffer port” ...
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... The CRC is recalculated for both tag insertion and tag removal. 802.1p priority field re-mapping is a QoS feature that allows the KSZ8842-PMQL/PMBL to set the “User Priority Ceiling” at any ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority field of the ingress port, the packet’ ...
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... Use the static table to assign a dedicated MAC address to a specific port. When a unicast MAC address is not recorded in the static table also not learned in the dynamic MAC table. The KSZ8842-PMQL/PMBL includes an option that can filter or forward unicast packets for an unknown MAC address. This option is enabled by SGCR7[7]. ...
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... P2CR4 bit 8 =1, the port 2 far-end loop back path is illustrated in the Figure 11. Near-end (Remote) Loop back: Near-end (Remote) loop back is conducted at either PHY port 1 or PHY port 2 of the KSZ8842-PMQL/PMBL. The loop back path starts at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’ ...
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... Host Communication The descriptor lists and data buffers, collectively called the host communication, manage the actions and status related to RX and TX buffer management. Commands and signals that control the functional operation of the KSZ8842- PMQL/PMBL are also described. The KSZ8842-PMQL/PMBL and the driver communicate through the two data structures: Command and status registers (CSRs), and Descriptor Lists and Data Buffers ...
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... This bit is not valid for runt frames. This bit is valid only when last descriptor is set. 14 – 11 Reserved 10 – Frame Length Indicates the length, in bytes, of the received frame, including the CRC. This field is valid only when last descriptor is set and descriptor error is reset. October 2007 36 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... Reserved 10 – 0 RBS Receive Buffer Size Indicates the size, in bytes, of the receive data buffer. If the field is 0, the KSZ8842- PMQL/PMBL ignores this buffer and moves to the next descriptor. The buffer size must be a multiple of 4. The following table shows the RDES2 register bit fields. ...
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... Reserved 10 – 0 TBS Transmit Buffer Size Indicates the size, in bytes, of the transmit data buffer. If this field is 0, the KSZ8842-PMQL/PMBL ignores this buffer and moves to the next descriptor. The following table shows the TDES2 register bit fields. Bit Description Buffer Address Indicates the physical memory address of the buffer ...
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... The CFCS register is divided into two sections: a command register (CFCS[15:0]) and a status register (CFCS[31:16]). The command register provides control of the KSZ8842-PMQL/PMBL’s ability to generate and respond to PCI cycles. When 0 is written to this register, the KSZ8842-PMQL/PMBL logically disconnects from the PCI bus for all accesses except configuration accesses. ...
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... Reserved 0 Parity Error Response When set, the KSZ8842-PMQL/PMBL asserts fatal bus error after it detects a parity error. When reset, any detected parity error is ignored and the KSZ8842- PMQL/PMBL continues normal operation. Parity checking is disabled after hardware reset. 000 Reserved 40 KSZ8842-PMQL/PMBL ...
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... Micrel, Inc. Bit Type 2 Command 1 Command 0 Reserved Configuration Revision Register (CFRV Offset 08H) The CFRV register contains the KSZ8842-PMQL/PMBL revision number. The following table shows the CFRV register bit fields. Bit Default 31 – 24 0x02 23 – 16 0x00 15 – 8 0x00 7 – 4 0x1 3 – 0 ...
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... Micrel, Inc. Configuration Base Memory Address Register (CBMA Offset 10H) The CBMA register specifies the base memory address for accessing the KSZ8842-PMQL/PMBL CSRs. This register must be initialized prior to accessing any CSR with memory access. The following table shows the CBMA register bit fields. ...
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... Value after hardware reset PCI Control & Status Registers The PCI CSR registers are all 32 bit in Little Endian format. For PCI register Read cycle, the KSZ8842-PMQL/PMBL allows any different combination of CBEN. For PCI register bus cycles, only byte, word (16-bit), or Dword (32-bit) accesses are allowed ...
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... October 2007 Description MTFCE MAC Transmit Flow Control Enable When this bit is set, flow control is enabled. This causes the KSZ8842- PMQL/PMBL to transmit a PAUSE frame from DMA to switch host MAC when the Receive Buffer has reached threshold and this bit is enabled. (SGCR3 bit 5 also needs to be enabled) ...
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... MAC additional Station Address and the MAC address register if they are set by user. MRE MAC DMA Receive Error Frame When set, the KSZ8842-PMQL/PMBL will pass the errors frames received to the host. Error frames include runt frames, oversized frames, CRC errors. MRA MAC DMA Receive All When set, the KSZ8842-PMQL/PMBL will receive all incoming frames, regardless of its destination address ...
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... Writing to this register is permitted only when its respective process is in the stopped state. When stopped, the register must be written before the respective START command is given. Note: The descriptor lists must be Word (32-bit) aligned. The KSZ8842-PMQL/PMBL behavior is unpredictable when the lists are not word-aligned. ...
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... When this bit is reset, the DMA MAC Receive Buffer Unavailable Interrupt is disabled. RW DMTPSIE DMA MAC Transmit Process Stopped Interrupt Enable When this bit is set, the DMA MAC Transmit Process Stopped Interrupt is enabled. When this bit is reset, the DMA MAC Transmit Process Stopped Interrupt is disabled. 47 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... DMTBUS DMA MAC Transmit Buffer Unavailable Status When this bit is set, it indicates that the next descriptor on the transmit list is owned by the host and cannot be acquired by the KSZ8842- PMQL/PMBL. The transmission process is suspended. To resume processing transmit descriptors, the host should change the ownership bit of the descriptor and then issue a transmit start command ...
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... The KSZ8842-PMQL/PMBL supports 16 additional MAC addresses for MAC address filtering. This MAC address is used to define one of the 16 destination addresses that the KSZ8842-PMQL/PMBL will respond to when receiving frames on the port. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are received left to right, and the bits within each byte are received right to left (LSB to MSB) ...
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... The register can be modified by the software driver, but will not modify the original MAC address value in the EEPROM. The MAC address is used to define the individual destination address that the KSZ8842- PMQL/PMBL host port will respond to when receiving unicast frames. This MAC address will become the source address when sending unicast frames from the host port to port-1 or port-2 ...
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... KSZ8842-PMQL/PMBL supports designs with and without an EEPROM system design. To support an external EEPROM, tie the EEPROM Enable (EEEN) pin/ball to High; otherwise, tie it to Low or no connect. The KSZ8842- PMQL/PMBL allows software to access (read and write) the EEPROM directly; that is, the EEPROM access timing can be fully controlled by the software if the EEPROM Software Access bit 4 in EEPCR is set ...
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... Global Soft Reset 1 = Software reset active 0 = Software reset inactive Set two times to finish the software reset, this soft reset bit will reset PCI control/status registers only. R/W Description RO Family ID Chip family RO Chip ID RO Revision ID RW Start Switch 1 = start the chip 52 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... After an age cycle is complete, the age logic will return to normal (300 + 75 seconds). Note: If any port is unplugged, all addresses will be automatically aged out. 53 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... This is to prevent the flow control port from being flow controlled for an extended period of time this mode flow control port and a non-flow control port talk to the same destination port, the flow control port will be flow controlled. This may not be “fair” to the flow control port. 54 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... NULL VID RW Broadcast storm protection rate Bit [10:8] These bits, along with SGCR3[15-8], determines how many “64-byte blocks” of packet data allowed on an input port in a preset period. The period is 67ms for 100Base-T or 670ms for 10Base-T. The default is 1%. 55 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... PxLED3 ACT PxLED2 LINK PxLED1 FULL_DPX/COL PxLED0 SPEED Port 1 and port 2 LED indicators as Repeater mode defined as follows: P1LED3 P1LED2 P1LED1 P1LED0 56 KSZ8842-PMQL/PMBL [0, 1] — 100LINK/ACT 10LINK/ACT FULL_DPX [1, 1] — — — — Switch Global Control Register 5: SGCR5 bit [15,9] [0,0] Default ...
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... IEEE Tag has a value of 0x1. RW Tag_0x0 IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE Tag has a value of 0x0. 57 KSZ8842-PMQL/PMBL Switch Global Control Register 5: SGCR5 bit [15,9] [0,0] Default [0,1] [1,0] [1,1] RPT_ACT — ...
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... R/W Description RW MACA[31:16] Specify host MAC address 2. This value must be the same as MAC Address Register Middle (0x0202): MARM. R/W Description RW MACA[15:0] Specify host MAC address 3. This value must be the same as MAC Address Register Low (0x0200): MARL. R/W Description RO Reserved 58 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x34. RW DSCP[25:24] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x30. RW DSCP[23:22] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x2C. 59 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x40. R/W Description RW DSCP[63:62] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x7C. RW DSCP[61:60] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x78. 60 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x88. RW DSCP[67:66] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x84. RW DSCP[65:64] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0x80. 61 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0xd0. RW DSCP[103:102] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0xcC. RW DSCP[101:100] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0xc8. 62 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... TOS/DiffServ/Traffic Class value is 0xe8. RW DSCP[115:114] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0xe4. RW DSCP[113:112] The value in this field is used as the frame’s priority when bits [7: TOS/DiffServ/Traffic Class value is 0xe0. R/W Description RO Reserved 63 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... Only for dynamic and statistics counter reads read is still in progress 0 = read has completed RO Reserved RO Indirect data. Bit 66-64 of indirect data R/W Description RW Indirect data Bit 47-32 of indirect data R/W Description RW Indirect data Bit 63-48 of indirect data R/W Description RW Indirect data Bit 15-0 of indirect data 64 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... Half duplex disabled (bit 12) RO Collision test Not supported RO Reserved R/W HP_mdix Auto MDIX mode 0 = Micrel Auto MDIX mode RW Force MDIX 1 = Force MDIX 0 = Normal operation 65 KSZ8842-PMQL/PMBL Is the same as: P1CR4, bit 8 P1CR4, bit 6 P1CR4, bit 7 P1CR4, bit 11 P1CR4, bit 13 P1CR4, bit 5 P1SR, bit 15 P1CR4, bit 9 M9999-100207-1.5 ...
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... Far end fault 1 = Far end fault detected far end fault detected RO AN capable 1 = Auto-negotiation capable 0 = Not auto-negotiation capable RO Link status 1 = Link Link is down 66 KSZ8842-PMQL/PMBL Is the same as: P1CR4, bit 10 P1CR4, bit 12 P1CR4, bit 14 P1CR4, bit 15 Is the same as: Always 1 Always 1 Always 1 Always 1 P1SR, bit 6 ...
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... Adv 10 Full 1 = Advertise 10 full duplex ability not advertise 10 full duplex ability RW Adv 10 Half 1 = Advertise 10 half duplex ability not advertise 10 half duplex ability RO Selector field 802.3 67 KSZ8842-PMQL/PMBL Is the same as: Is the same as: P1CR4, bit 4 P1CR4, bit 3 P1CR4, bit 2 P1CR4, bit 1 P1CR4, bit 0 M9999-100207-1.5 ...
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... Mbps disabled (bit 12 enable 1 = Auto-negotiation enabled 0 = Auto-negotiation disabled RW Power down 1 = Power down the PHY Normal operation RO Isolate Not supported 68 KSZ8842-PMQL/PMBL Is the same as: P1SR, bit 4 P1SR, bit 3 P1SR, bit 2 P1SR, bit 1 P1SR, bit 0 Is the same as: P2CR4, bit 8 P2CR4, bit 6 P2CR4, bit 11 M9999-100207-1.5 ...
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... RO 10 Full capable 1 = 10BaseT full duplex capable 0 = Not 10BaseT full duplex capable RO 10 Half capable 1 = 10BaseT half duplex capable 0 = Not 10BaseT half duplex capable 69 KSZ8842-PMQL/PMBL Is the same as: P2CR4, bit 13 P2CR4, bit 5 P2SR, bit 15 P2CR4, bit 9 P2CR4, bit 10 P2CR4, bit 12 P2CR4, bit 14 ...
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... High order PHYID bits R/W Description RO Next page Not supported RO Reserved RO Remote fault Not supported RO Reserved RW Pause 1 = Advertise pause ability not advertise pause ability RW Reserved 70 KSZ8842-PMQL/PMBL Is the same as: P2SR, bit 6 P2SR, bit 8 P2CR4, bit 7 P2SR, bit 5 Is the same as: P2CR4, bit 4 M9999-100207-1.5 ...
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... Adv 100 Half Link partner 100 half capability RO Adv 10 Full Link partner 10 full capability RO Adv 10 Half Link partner 10 half capability RO Reserved 71 KSZ8842-PMQL/PMBL Is the same as: P2CR4, bit 3 P2CR4, bit 2 P2CR4, bit 1 P2CR4, bit 0 Is the same as: P2SR, bit 4 P2SR, bit 3 P2SR, bit 2 P2SR, bit 1 P2SR, bit 0 M9999-100207-1 ...
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... Power Saving (pwrsave disable 0 = enable power saving RW Remote loop back (near end loop back ) 1 = Loop back at PMD/PMA of port 1’s PHY 0 = normal operation. RW Reserved 72 KSZ8842-PMQL/PMBL Is the same as: P1SCSLMD, bit 12 P1SCSLMD, bits 14-13 P1SCSLMD, bit 15 P1SCSLMD, bits the same as: P1SR, bit 13 P1SR, bit 7 ...
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... Enable power saving RW Remote loop back (near end loop back ) 1 = Loop back at PMD/PMA of port 2’s PHY 0 = normal operation. RW Reserved R/W Description RO Reserved 73 KSZ8842-PMQL/PMBL Is the same as: P2SCSLMD, bit 12 P2SCSLMD, bits 14-13 P2SCSLMD, bit 15 P2SCSLMD, bits the same as: P2SR, bit 13 P2SR, bit 7 P2SCSLMD, bit 11 ...
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... RW TX Multiple Queues Select Enable 1 = the port output queue is split into four priority queues single output queue on the port. There is no priority differentiation even though packets are classified into high or low priority. 74 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... VID Control register bits [15:13], replace the packet’s “user priority field” with the “user priority bits” in port 1’s VID Control register bits [15:13 not compare and replace the packet’s ‘user priority field” 75 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... Ingress and Egress rate limiting calculations IFG bytes are not counted RW Count Preamble bytes 1 = each frame’s preamble bytes (8 per frame) are included in Ingress and Egress rate limiting calculations preamble bytes are not counted 76 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
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... Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). 77 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 78
... Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). 78 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 79
... Not limited (Default) 0001 = 64 Kbps 0010 = 128 Kbps 0011 = 256 Kbps 0100 = 512 Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 79 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 80
... Output traffic from this priority queue is shaped according to the egress rate selected as shown below: 0000 = Not limited (Default) 0001 = 64 Kbps 0010 = 128 Kbps 0011 = 256 Kbps 0100 = 512 Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 80 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 81
... Disable 0 = Enable power saving RW Remote loop back 1 = Loop back at PMD/PMA of port 1’s PHY 0 = normal operation. RO VCT fault count Distance to the fault. The distance is approximately 0.4mXvct_fault_count 81 KSZ8842-PMQL/PMBL Is the same as: P1VCT, bit 12 P1VCT, bits 14-13 P1VCT, bit 15 P1PHYCTRL, bit 3 P1PHYCTRL, bit 2 P1PHYCTRL, bit 1 P1VCT, bits 8-0 M9999-100207-1 ...
Page 82
... AN is disabled (bit force 10Base disabled (bit 7) RW Force duplex 1 = force full duplex if ( disabled or ( enabled but failed force half duplex if ( disabled or ( enabled but failed. 82 KSZ8842-PMQL/PMBL Is the same as: P1MBCR, bit 0 P1MBCR, bit 1 P1MBCR, bit 9 P1MBCR, bit 2 P1MBCR, bit 11 P1MBCR, bit 3 P1MBCR, bit 4 ...
Page 83
... RO Operation duplex 1 = link duplex is full 0 = link duplex is half RO Far end fault 1 = Far end fault status detected Far end fault status detected 83 KSZ8842-PMQL/PMBL Is the same as: P1ANAR, bit 4 P1ANAR, bit 3 P1ANAR, bit 2 P1ANAR, bit 1 P1ANAR, bit 0 Is the same as: P1MBCR, bit 5 P1PHYCTRL, ...
Page 84
... RW Port based priority classification 00 = ingress packets on port 1 will be classified as priority 0 queue if “Diffserv” or “802.1p” classification is not enabled or fails to classify. 01 ingress packets on port 1 will be classified as priority 1 queue if 84 KSZ8842-PMQL/PMBL Is the same as: P1PHYCTRL,7 bit 4 P1MBSR, bit 5 P1MBSR, bit 2 P1ANLPR, bit 10 ...
Page 85
... Back pressure enable 1 = enable port’s half duplex back pressure 0 = disable port’s half duplex back pressure. RW Transmit enable 1 = enable packet transmission on the port 0 = disable packet transmission on the port RW Receive enable 1 = enable packet reception on the port 0 = disable packet reception on the port 85 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 86
... The Port can only communicate within the membership. An ‘1’ includes a port in the membership; an ‘0’ excludes a port from the membership. R/W Description RW User Priority bits Port 2 tag [15-13] for priority RW CFI bit Port 2 tag [12] for CFI RW VID bits Port 2 tag [11-0] for VID 86 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 87
... Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). 87 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 88
... Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). 88 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 89
... Not limited (Default) 0001 = 64 Kbps 0010 = 128 Kbps 0011 = 256 Kbps 0100 = 512 Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps 89 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 90
... Output traffic from this priority queue is shaped according to the egress rate selected as shown below: 0000 = Not limited (Default) 0001 = 64 Kbps 0010 = 128 Kbps 0011 = 256 Kbps 0100 = 512 Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 90 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 91
... Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). Note: When multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. 91 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 92
... Restart restart auto-negotiation 0 = normal operation RW Disable Far end fault 1 = disable far end fault detection & pattern transmission enable far end fault detection & pattern transmission. 92 KSZ8842-PMQL/PMBL Is the same as: P2VCT, bit 12 P2VCT, bits 14-13 P2VCT, bit 15 P2PHYCTRL, bit 3 P2PHYCTRL, bit 2 P2PHYCTRL, bit 1 ...
Page 93
... Full duplex capability from transmission to link partner RW Advertised 10BT half duplex capability 1 = advertise 10Base-T Half duplex capability 0 = suppress 10Base-T Half duplex capability from transmission to link partner 93 KSZ8842-PMQL/PMBL Is the same as: P2MBCR, bit 11 P2MBCR, bit 3 P2MBCR, bit 4 P2MBCR, bit 14 P2MBCR, bit 12 P2MBCR, bit 13 ...
Page 94
... RO Partner 10BT full duplex capability 1 = link partner 10Base-T full duplex capable 0 = link partner not 10Base-T full duplex capable 94 KSZ8842-PMQL/PMBL Is the same as: P2MBCR, bit 5 P2PHYCTRL, bit 5 P2MBCR, bit 4 P2PHYCTRL, ...
Page 95
... RW TX Multiple Queues Select Enable 1 = the port output queue is split into fourpriority queues single output queue on the port. There is no priority differentiation even though packets are classified into high or low priority. 95 KSZ8842-PMQL/PMBL Is the same as: P2ANLPR, bit 5 M9999-100207-1.5 ...
Page 96
... Define the port’s Port VLAN membership. Bit 2 stands for host port, bit 1 for port 2, and bit 0 for port 1. The Port can only communicate within the membership. An ‘1’ includes a port in the membership; an ‘0’ excludes a port from the membership. 96 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 97
... Ingress and Egress rate limiting calculations IFG bytes are not counted 0 RW Count Preamble bytes 1 = each frame’s preamble bytes (8 per frame) are included in Ingress and Egress rate limiting calculations preamble bytes are not counted 97 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 98
... Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). 98 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 99
... Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). 99 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 100
... Not limited (Default) 0001 = 64 Kbps 0010 = 128 Kbps 0011 = 256 Kbps 0100 = 512 Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 1100 = 64 Mbps 1101 = 72 Mbps 1110 = 80 Mbps 1111 = 88 Mbps 100 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 101
... Output traffic from this priority queue is shaped according to the egress rate selected as shown below: 0000 = Not limited (Default) 0001 = 64 Kbps 0010 = 128 Kbps 0011 = 256 Kbps 0100 = 512 Kbps 0101 = 1 Mbps 0110 = 2 Mbps 0111 = 4 Mbps 1000 = 8 Mbps 1001 = 16 Mbps 1010 = 32 Mbps 1011 = 48 Mbps 101 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 102
... Note: For 10Base-T, rate settings above 10Mbps are set to the default value 0000 (Not limited). Note: When multiple queue select enable is off (only 1 queue per port), rate limiting applies only to priority 0 queue. R/W Description RO Reserved R/W Description RO Reserved R/W Description RO Reserved R/W Description RO Reserved RO Reserved 102 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 103
... Micrel, Inc. MIB (Management Information Base) Counters The KSZ8842-PMQL/PMBL provides 32 MIB counters for port 1, port 2, and the host port. These counters are used to monitor the port activity for network management. The MIB counters are formatted “per port” as shown in Table 8, and “ ...
Page 104
... Successfully Tx frames on a port for which Tx is inhibited by more than one collision Description N/A Reserved RO Counter Value Description TX packets dropped due to lack of resources TX packets dropped due to lack of resources RX packets dropped due to lack of resources RX packets dropped due to lack of resources 104 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 105
... All Port Dropped Packet MIB counters are not cleared after they are accessed. The application needs to keep track of overflow and valid conditions on these counters. October 2007 // If bit 30 =0, restart (reread) from this register // If bit 30 =0, restart (reread) from this register 105 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 106
... Source Address (SA) look up, only the dynamic table is searched for aging, migration and learning purposes. The static DA look up result takes precedence over the dynamic DA look up result. If there match in both tables, the result from the static table is used. These entries in the static table will not be aged out by the KSZ8842- PMQL/PMBL. Bit Default 57 – ...
Page 107
... RO Time Stamp Specifies the 2-bit counter for internal aging. RO Source port Identifies the source port where FID+MAC is learned: 00, port 1 01, port 2 10, port 3 FID RO Specifies the filter ID. MAC Address RO Specifies the 48-bit MAC address. 107 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 108
... If 802.1Q VLAN mode is enabled, KSZ8842-PMQL/PMBL will assign a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non null VID, the VID in the tag will be used. The look up process will start from the VLAN table look up. If the VID is not valid, the packet will be dropped and no address learning will take place ...
Page 109
... OL 100Ω termination on the differential output. 100Ω termination on the differential output. Peak to peak 5MHz square wave DDATX 100Ω termination on the differential output. 100Ω termination on the differential output. 109 KSZ8842-PMQL/PMBL ( )...................... +3.1V to +3.5V DDATX DDARX DDIO )............ 0°C to +70° -40° ...
Page 110
... No (HS) heat spreader in this package. The thermal junction to ambient (θ 4. Specification for packaged product only. A single port’s transformer consumes an additional 45mA at 3.3V for 100BASE-T and 70mA at 3.3V for 10BASE-T. October 2007 ) and the thermal junction to case (θ JA 110 KSZ8842-PMQL/PMBL ) are under air velocity 0m/s. JC M9999-100207-1.5 ...
Page 111
... EESK EEDO 11 Hight-Z EEDI *1 Start bit Timing Parameter t cyc October 2007 D15 Figure 12. EEPROM Read Cycle Timing Diagram Description Min Clock cycle Setup time 20 Hold time 20 Table 15. EEPROM Timing Parameters 111 KSZ8842-PMQL/PMBL th D13 D14 D1 D0 Typ Max Unit 4000 M9999-100207-1.5 ...
Page 112
... October 2007 FLP FLP Burst Burst t FLPW t BTB Clock Data Pulse Pulse CTD t CTC Figure 13. Auto-Negotiation Timing Min 8 55.5 111 17 Table 16. Auto Negotiation Parameters 112 KSZ8842-PMQL/PMBL Clock Data Pulse Pulse Typ Max Unit 100 ns 64 69.5 µs 128 139 µs 33 M9999-100207-1.5 ...
Page 113
... Micrel, Inc. Reset Timing As long as the stable supply voltages to reset High timing (minimum of 10ms) are met, there is no power-sequencing requirement for the KSZ8842-PMQL/PMBL supply voltages 3.3V. The reset timing requirement is summarized in the Figure 14 and Table 17. Supply Voltage RST_N Symbol Parameter Stable supply voltages to reset High ...
Page 114
... Auto MDI-X H1102 H1260 HB726 S558-5999-U7 LF8505 LF-H41S TLA-6T718 Table 19. Qualified Single Port Magnetics Value 25 ± Table 20. Typical Reference Crystal Characteristics 114 KSZ8842-PMQL/PMBL Test Condition 100mV, 100kHz, 8mA 1MHz (min) 0MHz – 65MHz Number of Port Yes 1 Yes 1 Yes 1 Yes 1 Yes 1 Yes ...
Page 115
... Micrel, Inc. Package Information October 2007 Figure 15. 128-Pin PQFP 115 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 116
... Micrel, Inc. Package Information October 2007 Figure 16. 100-Ball LFBGA 116 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 117
... With auto MDI-X, the PHY senses the correct TX and RX roles, eliminating any cable confusion. The MIB comprises the management portion of network devices. This can include things like monitoring traffic levels and faults (statistical), 117 KSZ8842-PMQL/PMBL . CRC transmission errors using 80x86 processors ...
Page 118
... Commonly a cable containing 4 twisted pairs of wires. The wires are twisted in such a manner as to cancel electrical interference generated in each wire, therefore shielding is not required. A configuration of computers that acts as if all computers are connected by the same physical network but which may be located virtually anywhere. 118 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...
Page 119
... A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. October 2007 © 2007 Micrel, Incorporated. 119 KSZ8842-PMQL/PMBL M9999-100207-1.5 ...