IC DRIVER MOSF SYNC BUCK 55MLPQ

 

SIC417CD-T1-E3

Manufacturer Part NumberSIC417CD-T1-E3
DescriptionIC DRIVER MOSF SYNC BUCK 55MLPQ
ManufacturerVishay
SeriesmicroBUCK™
SIC417CD-T1-E3 datasheets

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Specifications of SIC417CD-T1-E3

TopologyStep-Down (Buck) Synchronous (1), Linear (LDO) (1)FunctionAny Function
Number Of Outputs2Frequency - Switching200kHz ~ 1MHz
Voltage/current - Output 10.5 V ~ 5.5 V, 10AVoltage/current - Output 20.75 V ~ 5.25 V, 150mA
W/led DriverNoW/supervisorNo
W/sequencerNoVoltage - Supply3 V ~ 28 V
Operating Temperature-25°C ~ 125°CMounting Type*
Package / Case*Output Voltage0.5 V to 5.5 V
Output Current10 AInput Voltage3 V to 28 V
Switching Frequency200 KHz to 1 MHzMounting StyleSMD/SMT
Duty Cycle (max)95 %Primary Input Voltage28V
No. Of Outputs1Voltage Regulator Case StyleMLPQ
No. Of Pins32Operating Temperature Range-25°C To +125°C
SvhcNo SVHCRohs CompliantYes
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
show all specifications
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SiC417
Vishay Siliconix
output is high and the low-side MOSFET is on. During this
time, the voltage across the inductor is approximately - V
This causes a down-slope or falling di/dt in the inductor. If the
load dI/dt is not much faster than the - dI/dt in the inductor,
then the inductor current will tend to track the falling load
current. This will reduce the excess inductive energy that
must be absorbed by the output capacitor, therefore a
smaller capacitance can be used.
The following can be used to calculate the needed
capacitance for a given dI
/dt:
LOAD
Peak inductor current is shown by the next equation.
I
= I
+ 1/2 x I
LPK
MAX
RIPPLEMAX
I
= 10 + 1/2 x 4.4 = 12.2 A
LPK
Rate of change of load current = dI
LOAD
I
= maximum load release = 10 A
MAX
I
I
LPK
MAX
L x
-
V
dl
OUT
C
= I
x
OUT
LPK
2 (V
- V
PK
Example
dl
2.5 A
LOAD
Load
=
dt
µs
This would cause the output current to move from 10 A to
zero in 4 µs as shown by the following equation.
12.2
0.88 µH x
-
1.05
C
= 12.2 x
OUT
2 (1.15 - 1.05)
C
= 379 µF
OUT
Note that C
is much smaller in this example, 379 µF
OUT
compared to 595 µF based on a worst-case load release. To
meet the two design criteria of minimum 379 µF and
maximum 9 mΩ ESR, select two capacitors rated at 220 µF
and 15 mΩ ESR.
It is recommended that an additional small capacitor be
placed in parallel with C
in order to filter high frequency
OUT
switching noise.
Stability Considerations
Unstable operation is possible with adaptive on-time
controllers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the FB
input or because the FB ripple voltage is too low. This causes
the FB comparator to trigger prematurely after the 250 ns
minimum off-time has expired. In extreme cases the noise
can
cause
three
or
more
successive
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not affect operation.
This form of instability can usually be avoided by providing
the FB pin with a smooth, clean ripple signal that is at least
10 mV
, which may dictate the need to increase the ESR of
p-p
the output capacitors. It is also imperative to provide a proper
PCB layout as discussed in the Layout Guidelines section.
www.vishay.com
14
.
OUT
V
OUT
/dt
Another way to eliminate doubling-pulsing is to add a small
(~ 10 pF) capacitor across the upper feedback resistor, as
x dt
LOAD
shown in figure 13. This capacitor should be left unpopulated
)
OUT
until it can be confirmed that double-pulsing exists. Adding
the C
TOP
eliminate the problem. An optional connection on the PCB
should be available for this capacitor.
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking
stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and ringing.
10
x 1 µs
Ringing for more than one cycle after the initial step is an
2.5
indication that the ESR should be increased.
One simple way to solve this problem is to add trace
resistance in the high current output path. A side effect of
adding trace resistance is output decreased load regulation.
ESR Requirements
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide10 mV
at the FB pin (after the resistor divider) to avoid double-
pulsing.
The second reason is to prevent instability due to insufficient
ESR. The on-time control regulates the valley of the output
ripple voltage. This ripple voltage is the sum of the two
voltages. One is the ripple generated by the ESR, the other
is the ripple due to capacitive charging and discharging
during the switching cycle. For most applications the
minimum ESR ripple voltage is dominated by the output
capacitors, typically SP or POSCAP devices. For stability the
ESR zero of the output capacitor should be lower than
approximately one-third the switching frequency. The
formula for minimum ESR is shown by the following
on-times.
equation.
For applications using ceramic output capacitors, the ESR is
normally too small to meet the above ESR criteria. In these
applications it is necessary to add a small virtual ESR
network composed of two capacitors and one resistor, as
shown in figure 14. This network creates a ramp voltage
C
TOP
To FB pin
R
1
R
2
Figure 13 - Capacitor Coupling to FB Pin
capacitor will couple more ripple into FB to help
3
ESR
=
MIN
2 x π x C
x f
OUT
SW
Document Number: 69062
S10-1367-Rev. D, 14-Jun-10
p-p

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