CP1W-20EDR1 Omron, CP1W-20EDR1 Datasheet - Page 19

• Manufacturer Part Number: CP1W-20EDR1
• Description: Expansion 12 In, 8 Out Relay
• Manufacturer: Omron

Specifications of CP1W-20EDR1

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32
CPU Unit Specifications
Note: The memory areas for CJ-series Special I/O Units and CPU Bus Units are allocated at the same as for the CJ-series. For details, refer to the CJ Series catalog
● CP1L
Item
Control method
I/O control method
Program language
Function blocks
Instruction length
Instructions
Instruction execution time
Common processing time
Program capacity
Number of tasks
Maximum subroutine number 256
Maximum jump number
I/O
areas
Work bits
TR Area
Holding Area
AR Area
Timers
Counters
DM Area
Data Register Area
Index Register Area
Task Flag Area
Trace Memory
Memory Cassette
Item
High-speed counters
Pulse outputs
(models with
transistor out-
puts only)
Built-in analog I/O terminals
Analog control
External analog input
(Cat. No. P052).
Scheduled inter-
rupt tasks
Input interrupt
tasks
Input bits
Output bits
1:1 Link Area
Serial PLC Link
Area
Pulse out-
puts
PWM out-
puts
Models
Models
Type
Type
Stored program method
Cyclic scan with immediate refreshing
Ladder diagram
Maximum number of function block definitions: 128 Maximum number of instances: 256
Languages usable in function block definitions: Ladder diagrams, structured text (ST)
1 to 7 steps per instruction
Approx. 500 (function codes: 3 digits)
Basic instructions: 0.55 μs min. Special instructions: 4.1 μs min.
0.4 ms
10K steps
288 (32 cyclic tasks and 256 interrupt tasks)
1 (interrupt task No. 2, fixed)
6 (interrupt task No. 140 to 145, fixed)
(Interrupt tasks can also be specified and executed for high-speed counter interrupts and executed.)
256
36: CIO 0.00 to CIO
0.11, CIO 1.00 to
CIO 1.11, and CIO
2.00 to CIO 2.11
24: CIO 100.00 to
CIO 100.07,
CIO 101.00 to CIO
101.07, and CIO
102.00 to CIO
102.07
1,024 bits (64 words): CIO 3000.00 to CIO 3063.15 (CIO 3000 to CIO 3063)
1,440 bits (90 words): CIO 3100.00 to CIO 3189.15 (CIO 3100 to CIO 3189)
8,192 bits (512 words): W000.00 to W511.15 (W0 to W511)
CIO Area: 37,504 bits (2,344 words): CIO 3800.00 to CIO 6143.15 (CIO 3800 to CIO 6143)
16 bits: TR0 to TR15
8,192 bits (512 words): H0.00 to H511.15 (H0 to H511)
Read-only (Write-prohibited): 7168 bits (448 words): A0.00 to A447.15 (A0 to A447)
Read/Write: 8192 bits (512 words): A448.00 to A959.15 (A448 to A959)
4,096 bits: T0 to T4095
4,096 bits: C0 to C4095
32 Kwords: D0 to D32767
16 registers (16 bits): DR0 to DR15
16 registers (32 bits): IR0 to IR15
32 flags (32 bits): TK0000 to TK0031
4,000 words (500 samples for the trace data maximum of 31 bits and 6 words.)
A special Memory Cassette (CP1W-ME05M) can be mounted. Note: Can be used for program backups and auto-booting.
4 inputs: Differential phases (4x), 50 kHz or
Trapezoidal or S-curve acceleration and deceleration
(Duty ratio: 50% fixed)
4 outputs, 1 Hz to 100 kHz (CCW/CW or pulse plus direction)
Duty ratio: 0.0% to 100.0% (Unit: 0.1%)
2 outputs, 0.1 to 1 kHz (Accuracy: ±5% at 1 kHz)
4 analog inputs and 2 analog
outputs
1 (Setting range: 0 to 255)
1 input (Resolution: 1/256, Input range: 0 to 10 V), not isolated
CP1L-M60@@-@
(60 points)
CP1L-M60
CP1H-XA CPU Units
CP1H-XA@@@-@
Single-phase (pulse plus direction, up/down, increment),
100 kHz
Value range: 32 bits, Linear mode or ring mode
Interrupts: Target value comparison or range comparison
24: CIO 0.00 to CIO
0.11 and CIO 1.00
to CIO 1.11
24: CIO 0.00 to CIO
0.11 and CIO 1.00
to CIO 1.11
CP1L-M40@@-@
(40 points)
CP1L-M40
None
CP1H-X CPU Units
18: CIO 0.00 to CIO
0.11 and CIO 1.00
to CIO 1.05
12: CIO 100.00 to
CIO 100.07 and
CIO 101.00 to CIO
101.03
CP1H-X@@@-@
CP1L-M30@@-@
(30 points)
CP1L-M30
5K steps
12: CIO 0.00 to CIO
0.11
8: CIO 100.00 to
CIO 100.07
10 Kwords: D0 to D9999, D32000 to D32767
CP1L-L20@@-@
(20 points)
CP1L-L20
2 inputs: Differential phases (4x),
2 inputs: Differential phases (4x), 50 kHz or Single-phase
Trapezoidal or S-curve acceleration and deceleration
(Duty ratio: 50% fixed)
2 outputs, 1 Hz to 1 MHz (CCW/CW or pulse plus
direction)
2 outputs, 1 Hz to 100 kHz (CCW/CW or pulse plus
direction)
Duty ratio: 0.0% to 100.0% (Unit: 0.1%)
2 outputs, 0.1 to 1 kHz (Accuracy: ±5% at 1 kHz)
500 kHz or Single-phase,
1 MHz and
(pulse plus direction, up/down, increment),
100 kHz
Value range: 32 bits, Linear mode or ring mode
Interrupts: Target value comparison or range
comparison
4 (interrupt task No.
140 to 143, fixed)
8: CIO 0.00 to CIO
0.07
6: CIO 100.00 to
CIO 100.05
CP1L-L14@@-@
CP1H-Y CPU Units
(14 points)
CP1L-L14
CP1H-Y@@@-@
2 (interrupt task No.
140 to 141, fixed)
6: CIO 0.00 to CIO
0.05
4: CIO 100.00 to
CIO 100.03
CP1L-L10@@-@
(10 points)
CP1L-L10