CQM1H-CTB41 Omron, CQM1H-CTB41 Datasheet - Page 9

• Manufacturer Part Number: CQM1H-CTB41
• Description: HS CTR INPUT,4 INPUT
• Manufacturer: Omron

Specifications of CQM1H-CTB41

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

J CPU UNIT SPECIFICATIONS
Characteristics
Item
Control method
I/O control method
Programming language
I/O capacity
Program capacity
User data memory capacity
Instruction length
Number of instructions
Instruction execution times
Overseeing time
Mounting structure
Mounting
CPU built-in DC input points
Maximum number of modules
Inner Boards
Communications modules
(Controller Link Module)
Types of
interrupts
I/O allocations
A--160
Input interrupts
(4 inputs max.)
Interval timer
interrupts
(3 timers max.)
High-speed counter
interrupts
Programmable Controller
Specifications
Stored program method
Cyclic scan and direct output/immediate interrupt processing
Ladder-diagram programming
CQM1H-CPU11/21: 256
CQM1H-CPU51/61: 512
CQM1H-CPU11/21 : 3.2 kwords
CQM1H-CPU51
CQM1H-CPU61
CQM1H-CPU11/21 : 3 kwords
CQM1H-CPU51
CQM1H-CPU61
1 step per instruction, 1 to 4 words per instruction
162 (14 basic, 148 special instructions)
Basic instructions: 0.375 to 1.125 µs
Special instructions: 17.7 µs (MOV instruction)
0.70 ms
No backplane (Modules are joined horizontally using connectors)
DIN Track mounting (screw mounting not possible)
16
Maximum of 11 modules total for I/O modules and Dedicated I/O modules
CQM1H-CPU11/21: None
CQM1H-CPU51/61: 2 Boards
CQM1H-CPU11/21: None
CQM1H-CPU51/61: 1 module
Input Interrupt Mode:
Interrupts are executed in response to inputs from external sources to the CPU’s built-in input
points.
Counter Mode:
Interrupts are executed in response to reception of a set number of pulses (counted down) via the
CPU’s internal built-in input points (4 points).
Scheduled Interrupt Mode:
Program is interrupted at regular intervals measured by one of the CPU’s internal timers.
One-shot Interrupt Mode:
An interrupt is executed after a set time, measured by one of the CPU’s internal timers.
Target Value Comparison:
Interrupt is executed when the high-speed counter PV is equal to a specified value.
Range Comparison:
Interrupt is executed when the high-speed counter PV lies within a specified range.
Counting is possible for high-speed counter inputs from the CPU’s internal input points, Pulse I/O
Boards, or Absolute Encoder Interface Boards. (The High-speed Counter Board has no interrupt
function, but can output bit patterns internally and externally.)
I/O is automatically allocated in order from the Unit nearest to the CPU. (Because there are no I/O
tables, it is not necessary to create I/O tables from a Programming Device.)
CQM1H
: 7.2 kwords
: 15.2 kwords
: 6 kwords
: 12 kwords (DM: 6 kwords; EM: 6 kwords)