MMDF2P02ER2G ON Semiconductor, MMDF2P02ER2G Datasheet - Page 5

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MMDF2P02ER2G

Manufacturer Part Number
MMDF2P02ER2G
Description
MOSFET PWR P-CH 25V 2.5A 8-SOIC
Manufacturer
ON Semiconductor
Datasheet

Specifications of MMDF2P02ER2G

Fet Type
2 P-Channel (Dual)
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
250 mOhm @ 2A, 10V
Drain To Source Voltage (vdss)
25V
Current - Continuous Drain (id) @ 25° C
2.5A
Vgs(th) (max) @ Id
3V @ 250µA
Gate Charge (qg) @ Vgs
15nC @ 10V
Input Capacitance (ciss) @ Vds
475pF @ 16V
Power - Max
2W
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MMDF2P02ER2G
Manufacturer:
ON/安森美
Quantity:
20 000
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
traverse any load line provided neither rated peak current
(I
transition time (t
total power averaged over a complete switching cycle must
not exceed (T
in switching circuits with unclamped inductive loads. For
DM
The Forward Biased Safe Operating Area curves define
Switching between the off−state and the on−state may
A power MOSFET designated E−FET can be safely used
100
) nor rated voltage (V
10
1
Figure 9. Resistive Switching Time Variation
V
I
V
T
D
J
DD
GS
= 2 A
= 25°C
= 10 V
= 10 V
J(MAX)
r
, t
f
) does not exceed 10 ms. In addition the
versus Gate Resistance
R
− T
G
, GATE RESISTANCE (OHMS)
t
t
d(on)
d(off)
C
)/(R
t
t
r
f
DSS
qJC
) is exceeded, and that the
10
).
di/dt = 300 A/ms
Figure 11. Reverse Recovery Time (t
SAFE OPERATING AREA
C
) of 25°C.
http://onsemi.com
MMDF2P02E
100
t, TIME
5
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
drain−to−source avalanche at currents up to rated pulsed
current (I
continuous current (I
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous I
assumed to equal the values indicated.
1.6
1.2
0.8
0.4
Although many E−FETs can withstand the stress of
2
0
0.6
Standard Cell Density
High Cell Density
t
a
T
VGS = 0 V
J
t
rr
= 25°C
DM
t
rr
t
V
Figure 10. Diode Forward Voltage
b
), the energy rating is specified at rated
SD
0.8
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
rr
)
versus Current
D
), in accordance with industry
1
1.2
D
1.4
can safely be
1.6

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