Audio CODECs Mono CODEC with Speaker Driver

WM8940GEFL/V

Manufacturer Part NumberWM8940GEFL/V
DescriptionAudio CODECs Mono CODEC with Speaker Driver
ManufacturerWolfson Microelectronics
WM8940GEFL/V datasheet
 


Specifications of WM8940GEFL/V

Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
Package / CaseQFN-24Minimum Operating Temperature- 25 C
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Mono CODEC with Speaker Driver
DESCRIPTION
The WM8940 is a low power, high quality mono CODEC
designed for portable applications such as digital still cameras
or camcorders.
The device integrates support for a differential or single ended
mic, and includes drivers for speakers or headphone, and
mono line output. External component requirements are
reduced as no separate microphone or headphone amplifiers
are required.
Advanced Sigma Delta Converters are used along with digital
decimation and interpolation filters to give high quality audio at
sample rates from 8 to 48ks/s. A selectable high pass filter
and four fully-programmable notch filters are available in the
ADC path. An advanced mixed signal ALC function with noise
gate is provided, while readback of PGA gain during ALC
operation is supported. The digital audio interface supports A-
law and µ-law companding.
An on-chip PLL is provided to generate the required Master
Clock from an external reference clock. The PLL clock can
also be output if required elsewhere in the system.
The WM8940 operates at supply voltages from 2.5 to 3.6V,
although the digital supplies can operate at voltages down to
1.71V to save power. Different sections of the chip can also be
powered down under software control using the selectable two
or three wire control interface.
WM8940 is supplied in a very small 4x4mm QFN package,
offering high levels of functionality in minimum board area,
with high thermal performance.
WOLFSON MICROELECTRONICS plc
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FEATURES
Mono CODEC:
Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz
DAC SNR 98dB, THD -84dB (‘A’-weighted @ 8 – 48ks/s)
ADC SNR 94dB, THD -80dB (‘A’-weighted @ 8 – 48ks/s)
On-chip Headphone/Speaker Driver
-
40mW output power into 16Ω
-
BTL speaker drive 0.4W into 8Ω
Additional MONO Line output
Multiple analog or ‘Aux’ inputs, plus analog bypass path
Mic Preamps:
Differential or single end Microphone Interface
-
Programmable preamp gain
-
Pseudo differential inputs with common mode rejection
-
Programmable ALC / Noise Gate in ADC path
Low-noise bias supplied for electret microphones
OTHER FEATURES
Digital Playback Limiter
Programmable high pass filter (wind noise reduction)
4 notch filters (narrowband noise suppression)
On-chip PLL
Low power, low voltage
-
2.5V to 3.6V (digital: 1.71V to 3.6V)
4x4x0.9mm 24 lead QFN package
APPLICATIONS
Digital still cameras and camcorders
General purpose mono audio CODEC
at
http://www.wolfsonmicro.com/enews/
WM8940
Production Data, Rev 4.2, April 2008
Copyright ©2008 Wolfson Microelectronics plc

WM8940GEFL/V Summary of contents

  • Page 1

    ... Low power, low voltage - 2.5V to 3.6V (digital: 1.71V to 3.6V) • 4x4x0.9mm 24 lead QFN package APPLICATIONS • Digital still cameras and camcorders • General purpose mono audio CODEC at http://www.wolfsonmicro.com/enews/ WM8940 Production Data, Rev 4.2, April 2008 Copyright ©2008 Wolfson Microelectronics plc ...

  • Page 2

    WM8940 BLOCK DIAGRAM w Production Data PD, Rev 4.2, April 2008 2 ...

  • Page 3

    Production Data DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................2 TABLE OF CONTENTS .........................................................................................3 PIN CONFIGURATION...........................................................................................5 ORDERING INFORMATION ..................................................................................5 PIN DESCRIPTION ................................................................................................6 ABSOLUTE MAXIMUM RATINGS.........................................................................7 RECOMMENDED OPERATING CONDITIONS .....................................................7 ELECTRICAL CHARACTERISTICS ......................................................................8 TERMINOLOGY .......................................................................................................... 10 AUDIO PATHS OVERVIEW .................................................................................11 SIGNAL ...

  • Page 4

    WM8940 NOTCH FILTER WORKED EXAMPLE........................................................................ 84 APPLICATIONS INFORMATION .........................................................................85 RECOMMENDED EXTERNAL COMPONENTS .......................................................... 85 PACKAGE DIAGRAM ..........................................................................................86 IMPORTANT NOTICE ..........................................................................................87 ADDRESS ................................................................................................................... 87 w Production Data PD, Rev 4.2, April 2008 4 ...

  • Page 5

    ... Production Data PIN CONFIGURATION TOP VIEW ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8940GEFL/V -25°C to +85°C WM8940GEFL/RV -25°C to +85°C Note: Reel Quantity = 3,500 w PACKAGE MOISTURE SENSITIVITY 24-lead QFN (4x4x0.9mm) (Pb-free) 24-lead QFN (4x4x0.9mm) (Pb-free, tape and reel) WM8940 PACKAGE BODY ...

  • Page 6

    WM8940 PIN DESCRIPTION PIN NAME MICBIAS Analogue Output 1 AVDD Supply 2 AGND Supply 3 DCVDD Supply 4 DBVDD Supply 5 Supply DGND 6 ADCDAT Digital Output 7 DACDAT Digital Input 8 FRAME Digital Input / Output 9 BCLK Digital ...

  • Page 7

    Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical ...

  • Page 8

    WM8940 ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD =3.3V, T stated. PARAMETER Microphone Input PGA Inputs (MICN, MICP) INPPGAVOL and PGABOOST = 0dB Full-scale Input Signal Level – Single- 1 ended input via LIN/RIN ...

  • Page 9

    Production Data Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD =3.3V, T stated. PARAMETER Digital to Analogue Converter (DAC) to MONO Output with 10kΩ / 50pF load and DACVOL 0dB 1 Full-scale output 3 Signal to Noise ...

  • Page 10

    WM8940 TERMINOLOGY 1. Full-scale input and output levels scale in relation to AVDD or SPKVDD depending upon the input or output used. For example, when AVDD = 3.3V, 0dBFS = 1V with a linear relationship to AVDD. 2. Input level ...

  • Page 11

    Production Data AUDIO PATHS OVERVIEW w WM8940 PD, Rev 4.2, April 2008 11 ...

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    WM8940 POWER CONSUMPTION Typical current consumption for various scenarios is shown below. MODE Power OFF (No Clocks) Sleep (VMID maintained, No Clocks) Mono Record (MIC input, +20dB gain, 8kHz, quiescent) SLAVE Mono Record (MIC input, +20dB gain, 44.1kHz, PLL, quiescent) ...

  • Page 13

    Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 1 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T PARAMETER System Clock Timing Information MCLK cycle time MCLK duty cycle Note 1: PLL pre-scaling and PLL N and ...

  • Page 14

    WM8940 Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information FRAME propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT ...

  • Page 15

    Production Data CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, T MCLK = ...

  • Page 16

    WM8940 CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low ...

  • Page 17

    Production Data DEVICE DESCRIPTION INTRODUCTION The WM8940 is a low power audio codec combining a high quality mono audio DAC and ADC, with flexible line and microphone input and output processing. Applications for this device include digital still cameras or ...

  • Page 18

    WM8940 CONTROL INTERFACES To allow full software control over all its features, the WM8940 supports wire control interface fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. ...

  • Page 19

    Production Data Figure 6 Microphone Input PGA Circuit (switch positions shown are for differential mic input) REGISTER ADDRESS R44 Input Control Table 2 Input Control The input PGA is enabled by the IPPGAEN register bit. REGISTER ADDRESS R2 Power Management ...

  • Page 20

    WM8940 INPUT PGA VOLUME CONTROL The input microphone PGA has a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the MICN input to the PGA output and from the AUX amplifier to the PGA output are ...

  • Page 21

    Production Data The AUXMODE register bit controls the auxiliary input mode of operation: In buffer mode (AUXMODE=0) the switch labelled AUXSW in Figure 7 is open and the signal at the AUX pin will be buffered and inverted through the ...

  • Page 22

    WM8940 REGISTER ADDRESS R45 Input PGA gain control R47 Input BOOST control Table 6 Input BOOST Stage Control The Auxiliary amplifier path to the BOOST stage is controlled by the AUX2BOOSTVOL[2:0] register bits. Settings 001 through to 111 control the ...

  • Page 23

    Production Data REGISTER R1 Power management 1 Table 9 Microphone Bias Enable REGISTER R44 Input Control Table 10 Microphone Bias Voltage Control The internal MICBIAS circuitry is shown in Figure 9. capability for MICBIAS is 3mA. The external biasing resistors ...

  • Page 24

    WM8940 Figure 10 ADC Digital Filter Path The ADC is enabled by the ADCEN register bit. REGISTER R2 Power management 2 Table 11 ADC Enable The polarity of the output signal can also be changed under software control using the ...

  • Page 25

    Production Data HPFCUT 000 001 010 011 100 101 110 111 Table 14 High Pass Filter Cut-off Frequencies (HPFAPP=1) Note that the High Pass filter values (when HPFAPP=1) work on the basis that the SR register bits are set correctly ...

  • Page 26

    WM8940 REGISTER ADDRESS R18 Notch Filter 1A R19 Notch Filter 1B Table 16 Notch Filter 1 Function REGISTER ADDRESS R20 Notch Filter 2A R21 Notch Filter 2B Table 17 Notch Filter 2 Function REGISTER ADDRESS R22 Notch Filter 3A R23 ...

  • Page 27

    Production Data Where: The actual register values can be determined from the coefficients as follows: To configure Notch Filter coefficients as follows: Where: The actual register values can be determined from the coefficients as follows: DIGITAL ...

  • Page 28

    WM8940 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8940 has an automatic PGA gain control circuit, which can function as an input peak limiter automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment ...

  • Page 29

    Production Data REGISTER ADDRESS R34 (22h) ALC Control 3 w BIT LABEL DEFAULT 7:4 ALCHLD 0000 [3:0] (0ms) 8 ALCMODE 0 7:4 ALCDCY 0011 [3:0] (26ms/6dB) 0011 (5.8ms/6dB) 3:0 ALCATK 0010 [3:0] (3.3ms/6dB) 0010 (726us/6dB) WM8940 DESCRIPTION ALC hold time ...

  • Page 30

    WM8940 REGISTER ADDRESS R42 (2Ah) ALC Control 4 Table 20 ALC Control Registers NOTE: The Input PGA Volume register R45 must be written with the INPPGAMUTE bit R45[6] set to 0 before setting ALCSEL bit R32[ When the ...

  • Page 31

    Production Data LIMITER MODE In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC ...

  • Page 32

    WM8940 NORMAL MODE ALCMODE = 0 (Normal Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 ALCMODE = 0 (Normal Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 21 ALC ...

  • Page 33

    Production Data LIMITER MODE ALCMODE = 1 (Limiter Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 ALCMODE = 1 (Limiter Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 22 ...

  • Page 34

    WM8940 MINIMUM AND MAXIMUM GAIN The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is ...

  • Page 35

    Production Data ALCMIN 000 001 010 011 100 101 110 111 Table 25 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or ...

  • Page 36

    WM8940 Figure 15 ALCLVL w Production Data PD, Rev 4.2, April 2008 36 ...

  • Page 37

    Production Data Figure 16 ALC Hold Time ALCHLD Table 27 ALC Hold Time Values w t (s) HOLD 0000 0 0001 2.67ms 0010 5.34ms 0011 10.7ms 0100 21.4ms 0101 42.7ms 0110 85.4ms 0111 171ms 1000 342ms 1001 684ms 1010 1.37s ...

  • Page 38

    WM8940 PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped ...

  • Page 39

    Production Data The diagrams below show the response of the system to the same signal with and without noise gate. Figure 17 ALC Operation Above Noise Gate Threshold w WM8940 PD, Rev 4.2, April 2008 39 ...

  • Page 40

    WM8940 Figure 18 Noise Gate Operation w Production Data PD, Rev 4.2, April 2008 40 ...

  • Page 41

    Production Data OUTPUT SIGNAL PATH The WM8940 output signal paths consist of digital application filters, up-sampling filters, a Hi-Fi DAC, analogue mixers, speaker and mono output drivers. The digital filters and DAC are enabled by bit DACEN. The mixers and ...

  • Page 42

    WM8940 HI-FI DIGITAL TO ANALOGUE CONVERTER (DAC) The DAC is enabled by the DACEN register bit. REGISTER R3 Power Management 3 Table 30 DAC Enable The WM8940 also has a Soft Mute function, which gradually attenuates the volume of the ...

  • Page 43

    Production Data DAC OUTPUT LIMITER The WM8940 has a digital output limiter function. The operation of this is shown in Figure 20. In this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows ...

  • Page 44

    WM8940 REGISTER ADDRESS R24 DAC digital limiter control 1 R25 DAC digital limiter control 2 w BIT LABEL DEFAULT 8 LIMEN 0 7:4 LIMDCY 0011 3:0 LIMATK 0010 6:4 LIMLVL 000 Production Data DESCRIPTION Enable the DAC digital limiter: 0=disabled ...

  • Page 45

    Production Data REGISTER ADDRESS Table 33 DAC Digital Limiter Control ANALOGUE OUTPUTS The WM8940 has a single MONO output and two outputs SPKOUTP and SPOUTN for driving a mono BTL speaker. These analogue output stages are supplied from SPKVDD and ...

  • Page 46

    WM8940 REGISTER ADDRESS R54 Speaker volume control Table 35 SPKOUT Volume Control ZERO CROSS TIMEOUT A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output PGAs the gain will automatically update ...

  • Page 47

    Production Data REGISTER ADDRESS R56 Mono mixer control Table 37 Mono Mixer Control ENABLING THE OUTPUTS Each analogue output of the WM8940 can be separately enabled or disabled. The analogue mixer associated with each output has a separate enable. All ...

  • Page 48

    WM8940 REGISTER ADDRESS R49 Table 39 Disabled Outputs to VREF Resistance A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 21. This buffer can be enabled using the BUFIOEN register bit. Table 40 ...

  • Page 49

    Production Data GPIOPOL Table 41 Output Switch Operation (GPIOSEL=001) THERMAL SHUTDOWN The speaker outputs can drive very large currents. To protect the WM8940 from overheating a thermal shutdown circuit is included. The ...

  • Page 50

    WM8940 HEADPHONE OUTPUT The speaker outputs can drive a 16Ω or 32Ω headphone load, either through DC blocking capacitors coupled without any capacitor. Headphone Output using DC Blocking Capacitors: Figure 23 Recommended Headphone Output Configurations When DC blocking ...

  • Page 51

    Production Data DIGITAL AUDIO INTERFACES The audio interface has four pins: • • • • The clock signals BCLK, and FRAME can be outputs when the WM8940 operates as a master, or inputs when slave (see Master ...

  • Page 52

    WM8940 Figure 26 Right Justified Audio Interface (assuming n-bit word length mode, the MSB is available on the second rising edge of BCLK following a FRAME transition. The other bits up to the LSB are then ...

  • Page 53

    Production Data LRC BCLK DACDAT / ADCDAT Figure 29 DSP/PCM Mode Audio Interface (Mode B, FRAMEP=1) AUDIO INTERFACE CONTROL The register bits controlling audio format, word length and master / slave mode are summarised below. Register bit MS selects audio ...

  • Page 54

    WM8940 REGISTER ADDRESS R5 Companding Control Table 43 Audio Interface Control Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the device will operate in 24-bit mode. REGISTER ADDRESS R6 Clock ...

  • Page 55

    Production Data LOOPBACK Setting the ADC_LOOPBACK or DAC_LOOPBACK register bit enables digital loopback. When the ADC_LOOPBACK bit is set the output data from the ADC audio interface is fed directly into the DAC data input. When the DAC_LOOPBACK bit is ...

  • Page 56

    WM8940 Figure 30 PLL and Clock Select Circuit The PLL frequency ratio controls the ratio of the division, and K the fractional part. The PLL output then passes through a fixed divide by 4, and can ...

  • Page 57

    Production Data INTEGER N DIVISION The integer division ratio (N) is determined by N[3:0] and must be in the range 5 to 12. If the PLL frequency is an exact integer (5,6,7,8,9,10,11,12) then FRAC_EN can be set to 0 for ...

  • Page 58

    WM8940 The PLL performs best when f are shown in Table 49. MCLK (MHz 14.4 14.4 19.2 19.2 19.68 19.68 19.8 19 Table 49 PLL Frequency Examples COMPANDING The WM8940 ...

  • Page 59

    Production Data Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: µ-law (where µ=255 for the U.S. and Japan): F( µ|x|) / ln( 1 ...

  • Page 60

    WM8940 Figure 32 A-Law Companding GENERAL PURPOSE INPUT/OUTPUT In 2-wire mode, the CSB pin is not required and it can be used as a GPIO pin wire mode, the MODE / GPIO can be configured as a GPIO ...

  • Page 61

    Production Data CONTROL INTERFACE SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS The control interface can operate as either a 3-wire or 2-wire interface. The MODE pin determines the wire mode as shown in Table 53. The ...

  • Page 62

    WM8940 REGISTER ADDRESS R8 GPIO control Table 54 Mode is GPIO Control Auto-incremental writes are supported in 2 wire and 3 wire modes. This is enabled by default. REGISTER ADDRESS R9 Control Interface Table 55 Control Interface 3-WIRE SERIAL CONTROL ...

  • Page 63

    Production Data Figure 36 Alternative 3-Wire Serial Control Timing A limited number of Readback addresses are provided to enable ALC operation to be monitored and to establish the identity and revision of the device. REGISTER ADDRESS R0 Software Reset R1 ...

  • Page 64

    WM8940 RESETTING THE CHIP The WM8940 can be reset by performing a write of any value to the software reset register (address 0 hex). This will cause all register values to be reset to their default values. In addition to ...

  • Page 65

    Production Data 14. 15. 16. 17. Power Down 10. Notes addition to the power on sequence recommended that the zero cross functions are used when changing ...

  • Page 66

    WM8940 POWER MANAGEMENT VMID The analogue circuitry will not work when VMID is disabled (VMIDSEL[1:0] = 00b). The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the start-up time of the ...

  • Page 67

    Production Data POP MINIMISATION Power-On-Bias Control (POB_CTRL) selects the bias current source for the output stages of the WM8940. 0 selects the VMID derived bias source (normal operation), 1 selects a non-VMID derived source which allows the output amplifiers to ...

  • Page 68

    WM8940 REGISTER MAP w Production Data PD, Rev 4.2, April 2008 68 ...

  • Page 69

    Production Data REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as “Reserved” should not be changed from the default. REGISTER BIT LABEL ADDRESS ...

  • Page 70

    WM8940 REGISTER BIT LABEL ADDRESS 7 MONOEN 6 SPKNEN 5 SPKPEN 4 Reserved 3 MONOMIXEN 2 SPKMIXEN 1 0 DACEN 4 (04h) 15:10 9 LOUTR 8 BCP 7 FRAMEP 6:5 WL 4:3 FMT 2 DLRSWAP 1 ALRSWAP w DEFAULT DESCRIPTION ...

  • Page 71

    Production Data REGISTER BIT LABEL ADDRESS 0 5 (05h) 15:7 6 DAC_LOOPBA CK 5 WL8 4:3 DAC_COMP 2:1 ADC_COMP 0 ADC_LOOPBA CK 6 (06h) 15:9 8 CLKSEL 7:5 MCLKDIV 4:2 BCLKDIV (07h) 15:7 w DEFAULT DESCRIPTION ...

  • Page 72

    WM8940 REGISTER BIT LABEL ADDRESS 6 POB_CTRL 5 SOFT_START 4 TOGGLE 3 SLOWCLKEN 8 (08h) 15:8 7 MODE_GPIO 6 5:4 OPCLKDIV 3 GPIOPOL 2:0 GPIOSEL 9 (09h) 15:2 1 AUTOINC 0 10 (0Ah) 15:7 w DEFAULT DESCRIPTION 0 ...

  • Page 73

    Production Data REGISTER BIT LABEL ADDRESS 6 DACMU 5:3 2 AMUTE 1 0 DACPOL 11 (0Bh) 15:8 7:0 DACVOL 12 (0Ch) 15:0 13 (0Dh) 15:0 14 (0Eh) 15:9 8 HPFEN 7 HPFAPP 6:4 HPFCUT 3:1 0 ADCPOL 15 (0Fh) 15:8 ...

  • Page 74

    WM8940 REGISTER BIT LABEL ADDRESS 13:0 NF0_A1 18 (12h) 15 NF1_UP 14 NF1_EN 13:0 NF1_A0 19 (13h) 15 NF1_UP 14 13:0 NF1_A1 20 (14h) 15 NF2_UP 14 NF2_EN 13:0 NF2_A0 21 (15h) 15 NF2_UP 14 13:0 NF2_A1 22 (16h) 15 ...

  • Page 75

    Production Data REGISTER BIT LABEL ADDRESS 8 LIMEN 24 (18h) 7:4 LIMDCY 3:0 LIMATK 25 (19h) 15:7 6:4 LIMLVL 3:0 LIMBOOST 26 (1Ah) 15:0 27 (1Bh) 15:0 w DEFAULT DESCRIPTION 0 Enable the DAC digital limiter: 0=disabled 1=enabled 0011 DAC ...

  • Page 76

    WM8940 REGISTER BIT LABEL ADDRESS 28 (1Ch) 15:0 29 (1Dh) 15:0 30 (1Eh) 15:0 31(1Fh) 15:0 32 (20h) 15:10 ALCGAIN [5: ALCSEL 7:6 5:3 ALCMAX 2:0 ALCMIN 33 (21h) 15:8 7:4 ALCHLD 3:0 ALCLVL 34 (22h) 15:9 8 ...

  • Page 77

    Production Data REGISTER BIT LABEL ADDRESS 3:0 PLLN[3:0] 37 (25h) 15:6 5:0 PLLK[23:18] 38 (26h) 15:9 8:0 PLLK[17:9] 39 (27h) 15:9 8:0 PLLK[8:0] 40 (28h) 15:0 41 (29h) 15:0 42 (2Ah) 15:2 1 ALCZC 0 43 (2Bh) 15:0 44 (2Ch) ...

  • Page 78

    WM8940 REGISTER BIT LABEL ADDRESS 5:0 INPPGAVOL 46 (2Eh) 15:0 47 (2Fh) 15:9 8 PGABOOST 7 6:4 MICP2BOOSTVOL 000 3 2:0 AUX2BOOSTVOL 000 48 (30h) 15:0 49 (31h) 15:2 1 TSDEN 0 VROI 50 (32h) 15:6 5 AUX2SPK 4:2 1 ...

  • Page 79

    Production Data REGISTER BIT LABEL ADDRESS 54 (36h) 15:9 8 SPKATTN 7 SPKZC 6 SPKMUTE 5:0 SPKVOL 55 (37h) 15:0 56 (38h) 15:8 7 MONOATTN 6 MONOMUTE 5:3 2 AUX2MONO 1 BYP2MONO 0 DAC2MONO w DEFAULT DESCRIPTION 00h Reserved 0 ...

  • Page 80

    WM8940 DIGITAL FILTER CHARACTERISTICS PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay ADC High Pass Filter High Pass Filter Corner Frequency DAC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Table 61 Digital Filter Characteristics TERMINOLOGY ...

  • Page 81

    Production Data DAC FILTER RESPONSES 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) Figure 38 DAC Digital Filter Frequency Response ADC FILTER RESPONSES 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency ...

  • Page 82

    WM8940 HIGHPASS FILTER The WM8940 has a selectable digital high pass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter 3.7Hz. frequency -10 -15 ...

  • Page 83

    Production Data NOTCH FILTERS AND LOW PASS FILTER The WM8940 supports four programmable notch filters. The fourth notch filter can be configured as a low pass filter. The following illustrates three digital notch filters, followed by a single low pass ...

  • Page 84

    WM8940 + -25 (dB) -30 -35 - 100 Figure 48 Cumulative Notch + Low Pass Filters Responses (48kHz); NF0 fc = 1kHz; NF1 fc = 5kHz; ...

  • Page 85

    Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 49 Recommended External Components w WM8940 PD, Rev 4.2, April 2008 85 ...

  • Page 86

    WM8940 PACKAGE DIAGRAM FL: 24 PIN QFN PLASTIC PACKAGE EXPOSED 6 GROUND PADDLE BOTTOM VIEW A3 C SIDE VIEW SEATING PLANE Exposed lead Half etch ...

  • Page 87

    ... Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...