WM8940GEFL/V Wolfson Microelectronics, WM8940GEFL/V Datasheet - Page 77

• Manufacturer Part Number: WM8940GEFL/V
• Description: Audio CODECs Mono CODEC with Speaker Driver
• Manufacturer: Wolfson Microelectronics

Specifications of WM8940GEFL/V

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-24
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

w
Production Data
37 (25h)
38 (26h)
39 (27h)
40 (28h)
41 (29h)
42 (2Ah)
43 (2Bh)
44 (2Ch)
45 (2Dh)
REGISTER
ADDRESS
3:0
15:6
5:0
15:9
8:0
15:9
8:0
15:0
15:0
15:2
1
0
15:0
15:9
8
7:4
3
2
1
0
15:8
7
6
BIT
PLLN[3:0]
PLLK[23:18]
PLLK[17:9]
PLLK[8:0]
ALCZC
MBVSEL
AUXMODE
AUX2INPPGA
MICN2INPPGA
MICP2INPPGA
INPPGAZC
INPPGAMUTE
LABEL
1100
001100
010010011
011101001
0000h
0000h
0 (zero
cross off)
0
0
0
1
0
000h
00h
00h
0
0
0000h
00h
0h
00h
0
1
DEFAULT
Integer (N) part of PLL input/output frequency ratio.
Use values greater than 5 and less than 13.
Reserved
Fractional (K) part of PLL1 input/output frequency ratio
(treat as one 24-digit binary number).
Reserved
Fractional (K) part of PLL1 input/output frequency ratio
(treat as one 24-digit binary number).
Reserved
Fractional (K) part of PLL1 input/output frequency ratio
(treat as one 24-digit binary number).
Reserved
Reserved
Reserved
ALC uses zero cross detection circuit.
0 = Disabled (recommended)
1 = Enabled
Reserved
Reserved
Reserved
Microphone Bias Voltage Control
0 = 0.9 * AVDD
1 = 0.75 * AVDD
Reserved
Auxiliary Input Mode
0 = inverting buffer
1 = mixer (on-chip input resistor bypassed)
Select AUX amplifier output as input PGA signal
source.
0=AUX not connected to input PGA
1=AUX connected to input PGA amplifier negative
terminal.
Connect MICN to input PGA negative terminal.
0=MICN not connected to input PGA
1=MICN connected to input PGA amplifier negative
terminal.
Connect input PGA amplifier positive terminal to MICP
or VMID.
0 = input PGA amplifier positive terminal connected to
VMID
1 = input PGA amplifier positive terminal connected to
MICP through variable resistor string
Reserved
Input PGA zero cross enable:
0=Update gain when gain register changes
1=Update gain on 1
write.
Mute control for input PGA:
0=Input PGA not muted, normal operation
1=Input PGA muted (and disconnected from the
following input BOOST stage).
DESCRIPTION
st
zero cross after gain register
PD, Rev 4.2, April 2008
Master Clock and
Phase Locked
Loop (PLL)
Master Clock and
Phase Locked
Loop (PLL)
Master Clock and
Phase Locked
Loop (PLL)
Master Clock and
Phase Locked
Loop (PLL)
ALC Control 4
Input Signal Path
Input Signal Path
Input Signal Path
Input Signal Path
Input Signal Path
Input Signal Path
Input Signal Path
REFER TO
WM8940
77