Audio CODECs Mono ADC Stereo DAC with Spkr

WM8976GEFL/V

Manufacturer Part NumberWM8976GEFL/V
DescriptionAudio CODECs Mono ADC Stereo DAC with Spkr
ManufacturerWolfson Microelectronics
WM8976GEFL/V datasheet
 


Specifications of WM8976GEFL/V

Mounting StyleSMD/SMTPackage / CaseQFN-32
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Stereo CODEC with Speaker Driver
DESCRIPTION
The WM8976 is a low power, high quality CODEC designed for
portable applications such as multimedia phone, digital still
camera or digital camcorder.
The device integrates a preamp for differential microphone, and
includes drivers for speakers, headphone and differential or
stereo line output. External component requirements are
reduced as no separate microphone or headphone amplifiers
are required.
Advanced on-chip digital signal processing includes a 5-band
equaliser, a mixed signal Automatic Level Control for the
microphone or line input through the ADC as well as a purely
digital limiter function for record or playback. Additional digital
filtering options are available in the ADC path, to cater for
application filtering such as ‘wind noise reduction’.
The WM8976 digital audio interface can operate as a master or
a slave. An internal PLL can generate all required audio clocks
for the CODEC from common reference clock frequencies, such
as 12MHz and 13MHz.
The WM8976 operates at analogue supply voltages from 2.5V to
3.3V, although the digital core can operate at voltages down to
1.71V to save power. The speaker outputs and OUT3/4 line
outputs can run from a 5V supply if increased output power is
required. Individual sections of the chip can also be powered
down under software control.
WOLFSON MICROELECTRONICS plc
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FEATURES
Stereo CODEC:
DAC SNR 98dB, THD -84dB (‘A’ weighted @ 48kHz)
ADC SNR 95dB, THD -84dB (‘A’ weighted @ 48kHz)
On-chip Headphone Driver with ‘capless’ option
-
40mW per channel into 16Ω / 3.3V SPKVDD
1W output power into 8Ω BTL speaker / 5V SPKVDD
-
Capable of driving piezo speakers
-
Stereo speaker drive configuration
Mic Preamps:
Differential or single-ended microphone interfaces
-
Programmable preamp gain
-
Pseudo differential input with common mode rejection
-
Programmable ALC / Noise Gate in ADC path
Low-noise bias supplied for electret microphone
Other Features:
Enhanced 3-D function for improved stereo separation
Digital playback limiter
5-band Equaliser (record or playback)
Programmable ADC High Pass Filter (wind noise reduction)
Programmable ADC Notch Filter
Aux inputs for stereo analog input signals or ‘beep’
On-chip PLL supporting 12, 13, 19.2MHz and other clocks
Support for 8, 11.025, 12, 16, 22.05, 24, 32, 44.1 and
48kHz sample rates
Low power, low voltage
-
2.5V to 3.6V (digital: 1.71V to 3.6V)
5x5mm 32-lead QFN package
APPLICATIONS
Stereo Camcorder or DSC
Multimedia Phone
http://www.wolfsonmicro.com/enews/
WM8976
Production Data, July 2009, Rev 4.4
Copyright ©2009 Wolfson Microelectronics plc

WM8976GEFL/V Summary of contents

  • Page 1

    ... Support for 8, 11.025, 12, 16, 22.05, 24, 32, 44.1 and 48kHz sample rates • Low power, low voltage - 2.5V to 3.6V (digital: 1.71V to 3.6V) • 5x5mm 32-lead QFN package APPLICATIONS • Stereo Camcorder or DSC • Multimedia Phone http://www.wolfsonmicro.com/enews/ WM8976 Production Data, July 2009, Rev 4.4 Copyright ©2009 Wolfson Microelectronics plc ...

  • Page 2

    WM8976 DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS ..................................................................................................... 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION .......................................................................................... 4 ORDERING INFORMATION .................................................................................. 4 PIN DESCRIPTION ................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS ........................................................................ 6 RECOMMENDED OPERATING CONDITIONS ..................................................... 6 ELECTRICAL CHARACTERISTICS ..................................................................... ...

  • Page 3

    Production Data RECOMMENDED EXTERNAL COMPONENTS ......................................................... 109 PACKAGE DIAGRAM ....................................................................................... 110 IMPORTANT NOTICE ....................................................................................... 111 ADDRESS ................................................................................................................... 111 w WM8976 PD Rev 4.4 July 2009 3 ...

  • Page 4

    ... WM8976 PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8976GEFL/V -25°C to +85°C WM8976GEFL/RV -25°C to +85°C Note: Reel quantity = 3,500 w PACKAGE MOISTURE SENSITIVITY LEVEL 32-lead QFN ( mm) (Pb-free) 32-lead QFN ( mm) (Pb-free, tape and reel) Production Data PEAK SOLDERING TEMPERATURE o MSL3 260 ...

  • Page 5

    Production Data PIN DESCRIPTION PIN NAME 1 LIP Analogue input Analogue input 2 LIN Analogue input 3 L2/GPIO2 4 DNC Do not connect 5 DNC Do not connect 6 DNC Do not connect Digital Input / Output 7 LRC Digital ...

  • Page 6

    WM8976 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics ...

  • Page 7

    Production Data ELECTRICAL CHARACTERISTICS Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD= 3.3V, T PARAMETER Microphone Preamp Inputs (LIP, LIN) Full-scale Input Signal Level – note this changes in proportion to AVDD (Note 1) Mic PGA equivalent input noise Input resistance MIC Programmable Gain ...

  • Page 8

    WM8976 Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD= 3.3V, T PARAMETER Digital to Analogue Converter (DAC) to Line-Out (LOUT1, ROUT1 with 10kΩ / 50pF load) Full-scale output Signal to Noise Ratio (Note 6) Total Harmonic Distortion (Note 7) Channel Separation (Note 9) Output ...

  • Page 9

    Production Data Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD= 3.3V, T PARAMETER OUT3/OUT4 outputs (with 10kΩ / 50pF load) Full-scale output voltage, 0dB gain (Note 9) Signal to Noise Ratio (Note 6) Total Harmonic Distortion (Note 7) Channel Separation (Note 8) Power Supply ...

  • Page 10

    WM8976 SPEAKER OUTPUT THD VERSUS POWER Speaker Power vs THD+N (8Ohm BTL Load) AVDD=SPKVDD=DBVDD=3.3, DCVDD=1.8 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.00 50.00 100.00 150.00 Speaker Power vs THD+N (8Ohm BTL Load) AVDD=DBVDD=3.3V, SPKVDD=5V, DCVDD=1.8V ...

  • Page 11

    Production Data POWER CONSUMPTION Typical current consumption for various scenarios is shown below. MODE Off Sleep (VREF maintained, no clocks) 2 MIC Record (8kHz) Stereo 16Ω HP Playback (48kHz, quiescent) Stereo 16Ω HP Playback (48kHz, white noise) Stereo 16Ω HP ...

  • Page 12

    WM8976 REGISTER BIT BUFDCOPEN OUT4MIXEN OUT3MIXEN PLLEN MICBEN BIASEN BUFIOEN VMIDSEL ROUT1EN LOUT1EN BOOSTENL INPPGAENL ADCENL OUT4EN OUT3EN LOUT2EN ROUT2EN RMIXEN LMIXEN DACENR DACENL Table 2 AVDD Supply Current (AVDD=3.3V) w AVDD CURRENT (mA) AVDD=3.3V 0.1 0.2 0.2 1.2 (with ...

  • Page 13

    Production Data AUDIO PATHS OVERVIEW Figure 1 WM8976 Audio Signal Paths w WM8976 PD Rev 4.4 July 2009 13 ...

  • Page 14

    WM8976 SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 2 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T PARAMETER System Clock Timing Information MCLK cycle time MCLK duty cycle Note 1: PLL pre-scaling and PLL N and K ...

  • Page 15

    Production Data Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information LRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT ...

  • Page 16

    WM8976 CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 5 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, T MCLK = 256fs, ...

  • Page 17

    Production Data CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 6 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK ...

  • Page 18

    WM8976 INTERNAL POWER ON RESET CIRCUIT Figure 7 Internal Power on Reset Circuit Schematic The WM8980 includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used reset the digital logic into a default state after power up. ...

  • Page 19

    Production Data Figure 9 Typical Power up Sequence where DVDD is Powered before AVDD Figure 9 shows a typical power-up sequence where DVDD comes up first. First it is assumed that DVDD is already up to specified operating voltage. When ...

  • Page 20

    WM8976 DEVICE DESCRIPTION INTRODUCTION The WM8976 is a low power audio CODEC combining a high quality stereo audio DAC and mono ADC, with flexible line and microphone input and output processing. Applications for this device include multimedia phones, digital camcorders, ...

  • Page 21

    Production Data OUT3 and OUT4 can be configured to provide an additional stereo lineout from the output of the DACs, the mixers or the input microphone boost stages. Alternatively OUT4 can be configured as a mono mix of left and ...

  • Page 22

    WM8976 INPUT SIGNAL PATH The WM8976 has flexible analogue inputs. An input PGA stage is followed by a boost/mix stage which drives into the hi-fi ADC. The input path has three input pins which can be configured in a variety ...

  • Page 23

    Production Data REGISTER ADDRESS R44 Input Control Table 5 Input PGA Control INPUT PGA VOLUME CONTROL The input microphone PGA has a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the LIN input to the PGA ...

  • Page 24

    WM8976 VOLUME UPDATES Volume settings will not be applied to the PGAs until a '1' is written to one of the INPPGAUPDATE bits. This is to allow left and right channels to be updated at the same time, as shown ...

  • Page 25

    Production Data Figure 13 Volume Update Using Zero Cross Detection If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8980 will automatically update the volume. The volume updates will occur between one and two ...

  • Page 26

    WM8976 The AUXL/R inputs can also be mixed into the output channel mixers, with a gain of -15dB to +6dB plus off. In addition the AUXR input can be summed into the Right speaker output path (ROUT2) with a gain ...

  • Page 27

    Production Data REGISTER ADDRESS R47 Input BOOST control Table 8 Input BOOST Stage Control The BOOST stage is enabled under control of the BOOSTEN register bit. REGISTER ADDRESS R2 Power management 2 Table 9 Input BOOST Enable Control MICROPHONE BIASING ...

  • Page 28

    WM8976 VMI Figure 16 Microphone Bias Schematic ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8976 uses a multi-bit, oversampled sigma-delta ADC. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC ...

  • Page 29

    Production Data The polarity of the output signal can also be changed under software control using the ADCLPOL register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when ADCOSR=1 the oversample rate is 128x ...

  • Page 30

    WM8976 PROGRAMMABLE NOTCH FILTER A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. The coefficients must be entered in 2’s complement notation. A0 and a1 are represented ...

  • Page 31

    Production Data NOTCH FILTER WORKED EXAMPLE The following example illustrates how to calculate the a0 and a1 coefficients for a desired centre frequency and -3dB bandwidth 1000 100 48000 ...

  • Page 32

    WM8976 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8976 has an automatic PGA gain control circuit, which can function as an input peak limiter automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment ...

  • Page 33

    Production Data REGISTER ADDRESS R34 (22h) ALC Control 3 w BIT LABEL DEFAULT 7:4 ALCHLD 0000 [3:0] (0ms) 8 ALCMODE 0 7:4 ALCDCY 0011 [3:0] (26ms/6dB) 0011 (5.8ms/6dB) 3:0 ALCATK 0010 [3:0] (3.3ms/6dB) 0010 (726us/6dB) WM8976 DESCRIPTION ALC hold time ...

  • Page 34

    WM8976 REGISTER ADDRESS Table 18 ALC Control Registers WHEN THE ALC IS DISABLED, THE INPUT PGA REMAINS AT THE LAST CONTROLLED VALUE OF THE ALC. AN INPUT GAIN UPDATE MUST BE MADE BY WRITING TO THE INPPGAVOLL/R REGISTER BITS. NORMAL ...

  • Page 35

    Production Data LIMITER MODE In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC ...

  • Page 36

    WM8976 ATTACK AND DECAY TIMES The attack and decay times set the update times for the PGA gain. The attack time is the time constant used when the gain is reducing. The decay time is the time constant used when ...

  • Page 37

    Production Data LIMITER MODE ALCMODE = 1 (Limiter Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 ALCMODE = 1 (Limiter Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 20 ...

  • Page 38

    WM8976 MINIMUM AND MAXIMUM GAIN The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is ...

  • Page 39

    Production Data ALCMIN 000 001 010 011 100 101 110 111 Table 23 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or ...

  • Page 40

    WM8976 Figure 21 ALCLVL w Production Data PD Rev 4.4 July 2009 40 ...

  • Page 41

    Production Data Figure 22 ALC Hold Time ALCHLD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 25 ALC Hold Time Values w t (s) HOLD 0 2.67ms 5.34ms 10.7ms 21.4ms 42.7ms 85.4ms 171ms 342ms 684ms 1.37s ...

  • Page 42

    WM8976 PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped ...

  • Page 43

    Production Data Figure 23 ALC Operation Above Noise Gate Threshold w WM8976 PD Rev 4.4 July 2009 43 ...

  • Page 44

    WM8976 Figure 24 Noise Gate Operation OUTPUT SIGNAL PATH The WM8976 output signal paths consist of digital application filters, up-sampling filters, stereo Hi-Fi DACs, analogue mixers, speaker, stereo headphone and stereo line/mono/midrail output drivers. The digital filters and DAC are ...

  • Page 45

    Production Data Figure 25 DAC Digital Filter Path The analogue outputs from the DACs can then be mixed with the aux analogue inputs and the ADC analogue inputs. The mix is fed to the output drivers for headphone (LOUT1/ROUT1), speaker ...

  • Page 46

    WM8976 The DAC output phase defaults to non-inverted. Setting DACPOLL will invert the DAC output phase on the left channel and DACPOLR inverts the phase on the right channel. AUTO-MUTE The DAC has an auto-mute function which applies an analogue ...

  • Page 47

    Production Data Figure 26 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 26, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter. ...

  • Page 48

    WM8976 REGISTER ADDRESS R24 DAC digital limiter control 1 R25 DAC digital limiter control 2 w BIT LABEL DEFAULT 3:0 LIMATK 0010 7:4 LIMDCY 0011 8 LIMEN 0 3:0 LIMBOOST 0000 Production Data DESCRIPTION Limiter Attack time (per 6dB gain ...

  • Page 49

    Production Data Table 30 DAC Digital Limiter Control 5-BAND GRAPHIC EQUALISER A 5-band graphic equaliser (EQ) is provided, which can be applied to the ADC or DAC path, together with 3D enhancement, under control of the EQ3DMODE register bit. REGISTER ...

  • Page 50

    WM8976 REGISTER ADDRESS R20 EQ Band 3 Control Table 34 EQ Band 3 Control REGISTER ADDRESS R21 EQ Band 4 Control Table 35 EQ Band 4 Control REGISTER ADDRESS R22 EQ Band 5 Gain Control Table 36 EQ Band 5 ...

  • Page 51

    Production Data 3D STEREO ENHANCEMENT The WM8976 has a digital 3D enhancement option to increase the perceived separation between the left and right channels. Selection of 3D for playback is controlled by register bit EQ3DMODE. Switching this bit from record ...

  • Page 52

    WM8976 Figure 27 Left/Right Output Channel Mixers w Production Data PD Rev 4.4 July 2009 52 ...

  • Page 53

    Production Data REGISTER ADDRESS R49 Output mixer control R50 Left channel output mixer control w BIT LABEL DEFAULT 5 DACR2LMIX 0 6 DACL2RMIX 0 0 DACL2LMIX 1 1 BYPL2LMIX 0 4:2 BYPLMIXVOL 000 5 AUXL2LMIX 0 8:6 AUXLMIXVOL 000 WM8976 ...

  • Page 54

    WM8976 REGISTER ADDRESS R51 Right channel output mixer control R3 Power management 3 Table 39 Left and Right Output Mixer Control HEADPHONE OUTPUTS (LOUT1 AND ROUT1) The headphone outputs, LOUT1 and ROUT1 can drive a 16Ω or 32Ω headphone load, ...

  • Page 55

    Production Data REGISTER ADDRESS R52 LOUT1 Volume control R53 ROUT1 Volume control Table 40 OUT1 Volume Control Headphone Output using DC Blocking Capacitors: Figure 29 Recommended Headphone Output Configurations When DC blocking capacitors are used, then their capacitance and the ...

  • Page 56

    WM8976 In the DC coupled configuration, the headphone “ground” is connected to the VMID pin. The OUT3/4 pins can be configured output driver by setting the OUT3MUTE and OUT4MUTE register bit. The DC voltage on VMID in ...

  • Page 57

    Production Data REGISTER ADDRESS R54 LOUT2 (SPK) Volume control R55 ROUT2 (SPK) Volume control Table 41 Speaker Volume Control The signal output on LOUT2/ROUT2 comes from the Left/Right Mixer circuits and can be any combination of the DAC output, the ...

  • Page 58

    WM8976 REGISTER ADDRESS R49 Output control R1 Power management 1 Table 42 Speaker Boost Stage Control SPKBOOST Table 43 Output Boost Stage Details REGISTER ADDRESS R43 Beep control Table 44 AUXR – ROUT2 BEEP Mixer Function ZERO CROSS TIMEOUT A ...

  • Page 59

    Production Data OUT3/OUT4 MIXERS AND OUTPUT STAGES The OUT3/OUT4 pins can provide an additional stereo line output, a mono output pseudo ground connection for headphones. There is a dedicated analogue mixer for OUT3 and one for OUT4 as ...

  • Page 60

    WM8976 REGISTER ADDRESS R56 OUT3 mixer control R57 OUT4 mixer control Table 46 OUT3/OUT4 Mixer Registers The OUT3 and OUT4 output stages each have a selectable gain boost of 1.5x (3.52dB). When this boost is enabled the output DC level ...

  • Page 61

    Production Data Figure 32 Outputs OUT3 and OUT4 REGISTER ADDRESS R49 Output control R1 Power management 1 Table 47 OUT3 and OUT4 Boost Stages Control OUT3BOOST/ OUT4BOOST Table 48 OUT3/OUT4 Output Boost Stage Details w BIT LABEL 3 OUT3BOOST 4 ...

  • Page 62

    WM8976 OUTPUT PHASING The relative phases of the analogue outputs will depend upon the following factors: 1. DACPOLL and DACPOLR invert bits: Setting these bits to 1 will invert the DAC output. 2. Mixer configuration: The polarity of the signal ...

  • Page 63

    Production Data Table 49 shows the polarities of the outputs in various configurations. Unless otherwise stated, polarity is shown with respect to left DAC output in non-inverting mode. Note that only registers relating to the mixer paths are shown here ...

  • Page 64

    WM8976 ENABLING THE OUTPUTS Each analogue output of the WM8976 can be separately enabled or disabled. The analogue mixer associated with each output has a separate enable. All outputs are disabled by default. To save power, unused parts of the ...

  • Page 65

    Production Data A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 34. This buffer can be enabled using the BUFIOEN register bit. If the SPKBOOST, OUT3BOOST or OUT4BOOST bits are set then the ...

  • Page 66

    WM8976 DIGITAL AUDIO INTERFACES The audio interface has four pins: • • • • The clock signals BCLK, and LRC can be outputs when the WM8976 operates as a master, or inputs when slave (see Master and ...

  • Page 67

    Production Data In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may ...

  • Page 68

    WM8976 In DSP/PCM mode, the left channel MSB is available on either the 1 edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency ...

  • Page 69

    Production Data REGISTER ADDRESS R4 Audio Interface Control Table 54 Audio Interface Control ADCLRSWAP bit controls whether the ADC data appears in the right or left phase of the LRC clock as defined for each audio format. Similarly, DACLRSWAP can ...

  • Page 70

    WM8976 REGISTER ADDRESS R6 Clock Generation Control Table 55 Clock Control The CLKSEL bit selects the internal source of the Master clock from the PLL (CLKSEL=1) or from MCLK (CLKSEL=0). When the internal clock is switched from one source to ...

  • Page 71

    Production Data AUDIO SAMPLE RATES The WM8976 sample rates for the ADC and the DACs are set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these values and ...

  • Page 72

    WM8976 Figure 40 PLL and Clock Select Circuit The PLL frequency ratio PLLN = int R PLLK = int (2 Note: The PLL is designed to operate with best performance (shortest lock time and optimum stability) when ...

  • Page 73

    Production Data R39 PLL K Value 3 Table 58 PLL Frequency Ratio Control The PLL performs best when f are shown in Table 59. MCLK DESIRED OUTPUT (MHz) (MHz) (F1) 12 11.29 90.3168 12 12.288 13 11.29 90.3168 13 12.288 ...

  • Page 74

    WM8976 REGISTER ADDRESS R5 Companding Control Table 60 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: μ-law (where μ=255 for the U.S. and Japan): F(x) ...

  • Page 75

    Production Data 120 100 Figure 41 u-Law Companding 120 100 Figure 42 A-Law Companding GENERAL PURPOSE INPUT/OUTPUT The WM8976 has two dual purpose input/output pins. • • The GPIO2 function is provided for use as a ...

  • Page 76

    WM8976 REGISTER ADDRESS R8 GPIO Control Table 62 CSB/GPIO Control Note: If MODE is set to 3 wire mode, CSB/GPIO1 shall be used as CSB input irrespective of the GPIO1SEL[2:] bits. Note that SLOWCLKEN must be enabled when using the ...

  • Page 77

    Production Data The VMID_EN signal has an OR function performed with the normal VMID driver enable. If the VMID_EN signal is to have no effect to normal functionality when jack detection is enabled, it should set to 0 for all ...

  • Page 78

    WM8976 3-WIRE SERIAL CONTROL MODE In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB/GPIO1 pin latches in a complete control word consisting of the last 16 bits. ...

  • Page 79

    Production Data POWER SUPPLIES The WM8976 can use up to four separate power supplies: AVDD and AGND: Analogue supply, powers all analogue functions except the speaker output and mono output drivers. AVDD can range from 2.5V to 3.6V and has ...

  • Page 80

    WM8976 RECOMMENDED POWER UP/DOWN SEQUENCE In order to powered up and down using one of the following sequences: Power-up when NOT using the output 1.5x boost stage: 1. Turn on external power supplies. Wait for supply voltage to settle. 2. ...

  • Page 81

    Production Data Notes: 1. This step enables the internal device bias buffer and the VMID buffer for unassigned inputs/outputs. This will provide a startup reference voltage for all inputs and outputs. This will cause the inputs and outputs to ramp ...

  • Page 82

    WM8976 Notes: 1. The analogue input pin charge time, t time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. 2. The analogue input pin discharge time, t capacitor ...

  • Page 83

    Production Data SYMBOL t line_midrail_on t line_midrail_off t hp_midrail_on t hp__midrail_off t dacint DAC Group Delay Table 66 Typical POR Operation (typical values, not tested) Notes: 1. The lineout charge time dependent upon the value of VMID decoupling ...

  • Page 84

    WM8976 POWER MANAGEMENT SAVING POWER BY REDUCING OVERSAMPLING RATE The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. 64x ...

  • Page 85

    Production Data REGISTER MAP REGISTER B8 ADDR NAME B[15:9] DEC HEX Software Reset 0 00 Power manage’t 1 BUFDCOP Power manage’t 2 ROUT1EN Power manage’t 3 OUT4EN 3 03 Audio Interface BCP ...

  • Page 86

    WM8976 ADC Boost ctrl PGABOOSTL 47 2F Output ctrl Left mixer ctrl 51 33 Right mixer ctrl 52 34 LOUT1 (HP) HPVU volume ctrl ROUT1 (HP HPVU volume ctrl 54 36 LOUT2 (SPK) ...

  • Page 87

    Production Data REGISTER BITS BY ADDRESS Notes 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as “Reserved” should not be changed from the default. REGISTER BIT LABEL ADDRESS ...

  • Page 88

    WM8976 REGISTER BIT LABEL ADDRESS 0 ADCENL 3 (03h) 8 OUT4EN 7 OUT3EN 6 LOUT2EN 5 ROUT2EN 3 RMIXEN 2 LMIXEN 1 DACENR 0 DACENL 4 (04h) 8 BCP 7 LRP 6:5 WL 4:3 FMT 2 DACLRSWAP w DEFAULT DESCRIPTION ...

  • Page 89

    Production Data REGISTER BIT LABEL ADDRESS 1 ADCLRSWAP 0 DACMONO 5 (05h) 8:6 5 WL8 4:3 DAC_COMP 2:1 ADC_COMP 0 LOOPBACK 6 (06h) 8 CLKSEL 7:5 MCLKDIV 4:2 BCLKDIV 1 w DEFAULT DESCRIPTION 0 Controls whether ADC data appears in ...

  • Page 90

    WM8976 REGISTER BIT LABEL ADDRESS (07h) 8:4 3 SLOWCLKEN 8 (08h) 8:6 5:4 OPCLKDIV 3 GPIO1POL 2:0 GPIO1SEL [2:0] 9 (09h) 8:7 JD_VMID 6 JD_EN 5 4 JD_SEL 3:0 10 (0Ah) 8:7 w DEFAULT DESCRIPTION ...

  • Page 91

    Production Data REGISTER BIT LABEL ADDRESS 6 SOFTMUTE 5:4 3 DACOSR128 2 AMUTE 1 DACPOLR 0 DACPOLL 11 (0Bh) 8 DACVU 7:0 DACVOLL 12 (0Ch) 8 DACVU 7:0 DACVOLR 13 (0Dh) 8 7:4 JD_EN1 3:0 JD_EN0 14 (0Eh) 8 HPFEN ...

  • Page 92

    WM8976 REGISTER BIT LABEL ADDRESS 6:4 HPFCUT 3 ADCOSR 128 2:1 0 ADCLPOL 15 (0Fh) 8 ADCVU 7:0 ADCVOLL 16 (10h) 8:0 18 (12h) 8 EQ3DMODE 7 6:5 EQ1C 4:0 EQ1G 19 (13h) 8 EQ2BW 7 6:5 EQ2C 4:0 EQ2G ...

  • Page 93

    Production Data REGISTER BIT LABEL ADDRESS 4:0 EQ3G 21 (15h) 8 EQ4BW 7 6:5 EQ4C 4:0 EQ4G 22 (16h) 8:7 6:5 EQ5C 4:0 EQ5G 24 (18h) 8 LIMEN 7:4 LIMDCY 3:0 LIMATK 25 (19h) 8:7 w DEFAULT DESCRIPTION 01100 EQ ...

  • Page 94

    WM8976 REGISTER BIT LABEL ADDRESS 6:4 LIMLVL 3:0 LIMBOOST 27 (1Bh) 8 NFU 7 NFEN 6:0 NFA0[13:7] 28 (1Ch) 8 NFU 7 6:0 NFA0[6:0] 29 (1Dh) 8 NFU 7 6:0 NFA1[13:7] 30 (1Eh) 8 NFU 7 6:0 NFA1[6:0] w DEFAULT ...

  • Page 95

    Production Data REGISTER BIT LABEL ADDRESS 32 (20h) 8 ALCSEL 7:6 5:3 ALCMAXGAIN 2:0 ALCMINGAIN 33 (21h) 8 7:4 ALCHLD 3:0 ALCLVL 34 (22h) 8 ALCMODE 7:4 ALCDCY [3:0] w DEFAULT DESCRIPTION 0 ALC function select: 0=ALC off 1=ALC on ...

  • Page 96

    WM8976 REGISTER BIT LABEL ADDRESS 3:0 ALCATK 35 (23h) 8:4 3 NGEN 2:0 NGTH 36 (24h) 8:5 4 PLL PRESCALE 3:0 PLLN[3:0] 37 (25h) 8:6 5:0 PLLK[23:18] 38 (26h) 8:0 PLLK[17:9] w DEFAULT DESCRIPTION Per step 0000 90.8us 0001 182us ...

  • Page 97

    Production Data REGISTER BIT LABEL ADDRESS 39 (27h) 8:0 PLLK[8:0] 40 (28h) 8:0 41 (29h) 8:4 3:0 DEPTH3D 43 (2Bh) 8:6 5 MUTERPGA 2INV 4 INVROUT2 3:1 BEEPVOL 0 BEEPEN 44 (2Ch) 8 MBVSEL 7:3 2 L2_2INP PGA 1 LIN2INP ...

  • Page 98

    WM8976 REGISTER BIT LABEL ADDRESS 5:0 INPPGA VOLL 46 (2Eh) 8:0 47 (2Fh) 8 PGA BOOSTL 7 6:4 L2_2 BOOSTVOL 3 2:0 AUXL2 BOOSTVOL 48 (30h) 8:0 49 (31h) 8:7 6 DACL2RMIX 5 DACR2LMIX 4 OUT4 BOOST 3 OUT3 BOOST ...

  • Page 99

    Production Data REGISTER BIT LABEL ADDRESS 0 VROI 50 (32h) 8:6 AUXLMIX VOL 5 AUXL2L MIX 4:2 BYPLMIX VOL 1 BYPL2L MIX 0 DACL2L MIX 51 (33h) 8:6 AUXRMIX VOL 5 AUXR2R MIX 4:1 0 DACR2R MIX 52 (34h) 8 ...

  • Page 100

    WM8976 REGISTER BIT LABEL ADDRESS 5:0 LOUT1VOL 53 (35h) 8 HPVU 7 ROUT1ZC 6 ROUT1 MUTE 5:0 ROUT1VOL 54 (36h) 8 SPKVU 7 LOUT2ZC 6 LOUT2 MUTE 5:0 LOUT2VOL 55 (37h) 8 SPKVU 7 ROUT2ZC 6 ROUT2 MUTE 5:0 ROUT2VOL ...

  • Page 101

    Production Data REGISTER BIT LABEL ADDRESS 3 OUT4_2OUT3 2 BYPL2OUT3 1 LMIX2OUT3 0 LDAC2OUT3 57 (39h) 8:7 6 OUT4MUTE 5 HALFSIG 4 LMIX2OUT4 3 LDAC2OUT4 2 1 RMIX2OUT4 0 RDAC2OUT4 w DEFAULT DESCRIPTION 0 OUT4 mixer output to OUT3 0 ...

  • Page 102

    WM8976 DIGITAL FILTER CHARACTERISTICS PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay ADC High Pass Filter High Pass Filter Corner Frequency DAC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Table 71 Digital Filter Characteristics TERMINOLOGY ...

  • Page 103

    Production Data DAC FILTER RESPONSES 20 0 -20 -40 -60 -80 -100 -120 -140 -160 0 0.5 1 Frequency (fs) Figure 47 DAC Digital Filter Frequency Response (128xOSR -20 -40 -60 -80 -100 -120 -140 -160 0 0.5 ...

  • Page 104

    WM8976 HIGHPASS FILTER The WM8976 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter applications mode the filter ...

  • Page 105

    Production Data 5-BAND EQUALISER The WM8976 has a 5-band equaliser which can be applied to either the ADC path or the DAC path. The plots from Figure 57 to Figure 70 show the frequency responses of each filter with a ...

  • Page 106

    WM8976 -10 - Frequency (Hz) Figure 62 EQ Band 3 – Peak Filter Centre Frequencies, EQ3B Figure -10 - ...

  • Page 107

    Production Data -10 - Frequency (Hz) Figure 65 EQ Band 4 – Peak Filter Centre Frequencies, EQ3B Figure -10 -15 -2 ...

  • Page 108

    WM8976 Figure 70 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with ±12dB gain. The red traces show the cumulative effect of all bands with ...

  • Page 109

    Production Data APPLICATION INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 71 Recommended External Component Diagram w WM8976 PD Rev 4.4 July 2009 109 ...

  • Page 110

    WM8976 PACKAGE DIAGRAM FL: 32 PIN QFN PLASTIC PACKAGE EXPOSED 6 GROUND PADDLE BOTTOM VIEW A3 C SIDE VIEW SEATING PLANE Exposed lead Half ...

  • Page 111

    ... Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...