WM8976GEFL/V Wolfson Microelectronics, WM8976GEFL/V Datasheet - Page 71

• Manufacturer Part Number: WM8976GEFL/V
• Description: Audio CODECs Mono ADC Stereo DAC with Spkr
• Manufacturer: Wolfson Microelectronics

Specifications of WM8976GEFL/V

• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
AUDIO SAMPLE RATES
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
w
Table 56 Sample Rate Control
The PLL can be enabled or disabled by the PLLEN register bit.
Note: In order to minimise current consumption, the PLL is disabled when the VMIDSEL[1:0] bits are
set to 00b. VMIDSEL[1:0] must be set to a value other than 00b to enable the PLL.
Table 57 PLLEN Control Bit
The WM8976 sample rates for the ADC and the DACs are set using the SR register bits. The cutoffs
for the digital filters and the ALC attack/decay times stated are determined using these values and
assume a 256fs master clock rate.
If a sample rate that is not explicitly supported by the SR register settings is required then the closest
SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay
and hold times will scale appropriately.
The WM8976 has an on-chip phase-locked loop (PLL) circuit that can be used to:
Generate master clocks for the WM8976 audio functions from another external clock, e.g. in
telecoms applications.
Generate and output (on pin CSB/GPIO1 and/or GPI04) a clock for another part of the system that is
derived from an existing audio master clock.
Figure 40 shows the PLL and internal clocki ecommendatent on the WM8976.
R7
Additional
Control
R1
Power
management 1
REGISTER
ADDRESS
REGISTER
ADDRESS
3:1
BIT
5
BIT
SR
LABEL
PLLEN
LABEL
000
0
DEFAULT
DEFAULT
PLL enable
0=PLL off
1=PLL on
Approximate sample rate (configures the
coefficients for the internal digital filters):
000=48kHz
001=32kHz
010=24kHz
011=16kHz
100=12kHz
101=8kHz
110-111=reserved
DESCRIPTION
DESCRIPTION
PD Rev 4.4 July 2009
WM8976
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