WM8976GEFL/V Wolfson Microelectronics, WM8976GEFL/V Datasheet - Page 96

Audio CODECs Mono ADC Stereo DAC with Spkr

WM8976GEFL/V

Manufacturer Part Number
WM8976GEFL/V
Description
Audio CODECs Mono ADC Stereo DAC with Spkr
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM8976GEFL/V

Mounting Style
SMD/SMT
Package / Case
QFN-32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
WM8976
w
35 (23h)
36 (24h)
37 (25h)
38 (26h)
REGISTER
ADDRESS
3:0
8:4
3
2:0
8:5
4
3:0
8:6
5:0
8:0
BIT
ALCATK
NGEN
NGTH
PLL
PRESCALE
PLLN[3:0]
PLLK[23:18]
PLLK[17:9]
LABEL
0010
0010
00000
0
000
0000
0
1000
000
01100
01001001
1
DEFAULT
ALC attack (gain ramp-down) time
0000
0001
0010
… (time doubles with every step)
1010
ALC attack (gain ramp-down) time
(ALCMODE == 0)
0000
0001
0010
… (time doubles with every step)
1010 or
higher
(ALCMODE == 1)
0000
0001
0010
… (time doubles with every step)
1010
Reserved
ALC Noise gate function enable
1 = enable
0 = disable
ALC Noise gate threshold:
000=-39dB
001=-45dB
010=-51db
… (6dB steps)
111=-81dB
Reserved
0 = MCLK input not divided (default)
1 = Divide MCLK by 2 before input to PLL
Integer (N) part of PLL input/output frequency ratio.
Use values greater than 5 and less than 13.
Reserved
Fractional (K) part of PLL1 input/output frequency
ratio (treat as one 24-digit binary number).
Fractional (K) part of PLL1 input/output frequency
ratio (treat as one 24-digit binary number).
Per step
90.8us
182us
363us
93ms
Per step
104us
208us
416us
106ms
Per step
22.7us
45.4us
90.8us
23.2ms
DESCRIPTION
Per 6dB
726us
1.45ms
2.91ms
744ms
Per 6dB
832us
1.66ms
3.33ms
852ms
Per 6dB
182us
363us
726us
186ms
90% of
range
5.23ms
10.5ms
20.9ms
5.36s
90% of
range
6ms
12ms
24.1ms
6.13s
90% of
range
1.31ms
2.62ms
5.23ms
1.34s
PD Rev 4.4 July 2009
Input Limiter/
Automatic
Level Control
(ALC)
Input Limiter/
Automatic
Level Control
(ALC)
Input Limiter/
Automatic
Level Control
(ALC)
Master Clock
and Phase
Locked Loop
(PLL)
Master Clock
and Phase
Locked Loop
(PLL)
Master Clock
and Phase
Locked Loop
(PLL)
Master Clock
and Phase
Locked Loop
(PLL)
REFER TO
Production Data
96

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