WM8976GEFL/V Wolfson Microelectronics, WM8976GEFL/V Datasheet - Page 97

Audio CODECs Mono ADC Stereo DAC with Spkr

WM8976GEFL/V

Manufacturer Part Number
WM8976GEFL/V
Description
Audio CODECs Mono ADC Stereo DAC with Spkr
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM8976GEFL/V

Mounting Style
SMD/SMT
Package / Case
QFN-32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Production Data
w
39 (27h)
40 (28h)
41 (29h)
43 (2Bh)
44 (2Ch)
45 (2Dh)
REGISTER
ADDRESS
8:0
8:0
8:4
3:0
8:6
5
4
3:1
0
8
7:3
2
1
0
8
7
6
BIT
PLLK[8:0]
DEPTH3D
MUTERPGA
2INV
INVROUT2
BEEPVOL
BEEPEN
MBVSEL
L2_2INP
PGA
LIN2INP
PGA
LIP2INP
PGA
INPPGA
UPDATE
INPPGAZCL
INPPGA
MUTEL
LABEL
01110100
1
00000000
0
00000
0000
000
0
0
000
0
0
00000
0
1
1
N/A
0
0
DEFAULT
INPPGAVOLL and INPPGAVOLR volume do not
Fractional (K) part of PLL1 input/output frequency
ratio (treat as one 24-digit binary number).
Reserved
Reserved
Stereo depth
0000: 0% (minimum 3D effect)
0001: 6.67%
....
1110: 93.3%
1111: 100% (maximum 3D effect)
Reserved
Mute input to INVROUT2 mixer
Mute input to INVROUT2 mixer
AUXR input to ROUT2 inverter gain
000 = -15dB
...
111 = +6dB
0 = mute AUXR beep input
1 = enable AUXR beep input
Microphone Bias Voltage Control
0 = 0.9 * AVDD
1 = 0.6 * AVDD
Reserved
Connect L2 pin to input PGA positive terminal.
0=L2 not connected to input PGA
1=L2 connected to input PGA amplifier positive
terminal (constant input impedance).
Connect LIN pin to input PGA negative terminal.
0=LIN not connected to input PGA
1=LIN connected to input PGA amplifier negative
terminal.
Connect LIP pin to input PGA amplifier positive
terminal.
0 = LIP not connected to input PGA
1 = input PGA amplifier positive terminal
connected to LIP (constant input impedance)
update until a 1 is written to INPPGAUPDATE (in
reg 45 or 46)
Input PGA zero cross enable:
0=Update gain when gain register changes
1=Update gain on 1
write.
Mute control for input PGA:
0=Input PGA not muted, normal operation
1=Input PGA muted (and disconnected from the
following input BOOST stage).
DESCRIPTION
st
zero cross after gain register
PD Rev 4.4 July 2009
Master Clock
and Phase
Locked Loop
(PLL)
3D Stereo
Enhancement
Analogue
Outputs
Analogue
Outputs
Analogue
Outputs
Analogue
Outputs
Input Signal
Path
Input Signal
Path
Input Signal
Path
Input Signal
Path
Input Signal
Path
Input Signal
Path
Input Signal
Path
REFER TO
WM8976
97

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