WM8990ECS/RV

Manufacturer Part NumberWM8990ECS/RV
DescriptionAudio CODECs Stereo CODEC w.Class AB/D speaker driver
ManufacturerWolfson Microelectronics
WM8990ECS/RV datasheet
 


Specifications of WM8990ECS/RV

Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Mobile Multimedia CODEC with
Dual-Mode Class AB/D Speaker Driver
DESCRIPTION
The WM8990 is a highly integrated ultra-low power hi-fi codec
designed for handsets rich in multimedia features such as
mobile TV, digital audio playback and gaming. Ultra-low power
and low noise interfaces to many other audio components in the
system are provided.
A powerful 1W speaker driver can operate in class D or AB
modes, providing total flexibility to the system designer. Low
leakage, high PSRR and pop/click suppression enable direct
battery connection for the speaker supply.
A very highly flexible input configuration supports multiple
microphone or line inputs (mono or stereo, single-ended or
differential).
Four headphone drivers support fully differential headset drive,
providing excellent crosstalk performance and bass response,
maximising stereo effects, and allowing the removal of large
and expensive headphone capacitors.
Stereo 24-bit sigma-delta ADCs and DACs provide hi-fi quality
audio record and playback, with a flexible digital audio interface
supporting
most
commonly-used
integrated low power PLL, an alternative DAC interface and
TDM support provide additional flexibility.
The WM8990 is supplied in very small and thin 42-ball WCSP
package, ideal for portable systems.
WOLFSON MICROELECTRONICS plc
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FEATURES
DAC SNR 99dB (‘A’ weighted), THD -84dB at 48kHz, 3.3V
ADC SNR 94dB (‘A’ weighted), THD -82dB at 48kHz, 3.3V
Microphone interface (Up to four differential microphones)
1W Speaker driver
-
1W into 8Ω BTL speaker at <0.1% THD
-
80dB PSRR @217Hz
-
<1uA leakage with direct battery connection
-
Software-selectable class D or AB mode
-
Filterless connection supported
-
Pop/Click suppression
Headphone / ear speaker drivers
-
40mW output power into 16Ω at 3.3V
-
Fully differential and capless modes supported
-
Pop/Click suppression
4 Mono or stereo differential line outputs
Powerful GPIO functions
Ultra-low power consumption
-
8.3mW analogue voice call
-
13.7mW DAC playback to headphones
On-chip PLL provides flexible clocking scheme
Sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48kHz
clocking
schemes.
An
42-ball W-CSP package (3.226x3.44x0.7mm, 0.5mm pitch)
APPLICATIONS
Multimedia phones
GPS
http://www.wolfsonmicro.com/enews/
WM8990
Production Data, March 2009, Rev 4.0
Copyright ©2009 Wolfson Microelectronics plc

WM8990ECS/RV Summary of contents

  • Page 1

    ... On-chip PLL provides flexible clocking scheme • Sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48kHz clocking schemes. An • 42-ball W-CSP package (3.226x3.44x0.7mm, 0.5mm pitch) APPLICATIONS • Multimedia phones • GPS http://www.wolfsonmicro.com/enews/ WM8990 Production Data, March 2009, Rev 4.0 Copyright ©2009 Wolfson Microelectronics plc ...

  • Page 2

    WM8990 DESCRIPTION ....................................................................................................... 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 TABLE OF CONTENTS ......................................................................................... 2 BLOCK DIAGRAM ................................................................................................. 4 PIN CONFIGURATION ........................................................................................... 5 ORDERING INFORMATION .................................................................................. 5 PIN DESCRIPTION ................................................................................................ 6 ABSOLUTE MAXIMUM RATINGS ......................................................................... 8 RECOMMENDED OPERATING CONDITIONS ..................................................... 8 ...

  • Page 3

    Production Data DIGITAL FILTER CHARACTERISTICS ............................................................. 164 ADC FILTER RESPONSES ....................................................................................... 165 ADC HIGH PASS FILTER RESPONSES ................................................................... 165 DAC FILTER RESPONSES ....................................................................................... 166 DE-EMPHASIS FILTER RESPONSES ...................................................................... 167 APPLICATIONS INFORMATION ....................................................................... 168 RECOMMENDED EXTERNAL COMPONENTS ......................................................... 168 PACKAGE DIMENSIONS ...

  • Page 4

    WM8990 BLOCK DIAGRAM -1 w Production Data -1 CSB/ADDR SDIN SCLK MODE MCLK GPIO5/DACDAT2 GPIO4/DACLRC2 GPIO3/BCLK2 ADCLRC/GPIO1 ADCDAT DACDAT DACLRC BCLK DGND DCVDD DBVDD HPVDD HPGND SPKVDD SPKGND AVDD VMID AGND PD, March 2009, Rev 4.0 4 ...

  • Page 5

    ... Production Data PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8990ECS/RV -40°C to +85°C Note: Reel quantity = 3500 w PACKAGE MOISTURE SENSITIVITY LEVEL 42-ball W-CSP MSL3 (Pb-free, Tape and reel) WM8990 PEAK SOLDERING TEMPERATURE 260°C PD, March 2009, Rev 4.0 5 ...

  • Page 6

    WM8990 PIN DESCRIPTION PIN NO NAME A2 MICBIAS Analogue Output Analogue Input D3 LIN1 C5 LIN2 Analogue Input C6 LIN3 / Analogue Input / GPI7 Digital Input B6 LIN4 / Analogue Input RXN D4 RIN1 Analogue Input D6 RIN2 Analogue ...

  • Page 7

    Production Data PIN NO NAME C3 VMID Analogue Output G2 GPIO3 / Digital Input / Output BCLK2 G3 GPIO4 / Digital Input / Output DACLRC2 Digital Input / Output G1 GPIO5 / DACDAT2 w TYPE Midrail voltage decoupling capacitor Alternative ...

  • Page 8

    WM8990 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics ...

  • Page 9

    Production Data THERMAL PERFORMANCE Thermal analysis should be performed in the intended application to prevent the WM8990 from exceeding maximum junction temperature. Several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of the ...

  • Page 10

    WM8990 SPEAKER POWER DE-RATING CURVE The speaker driver has been designed to drive a maximum of 1W into 8Ω with a 5V supply. However, thermal restrictions defined by the W-CSP package Ө be safely dissipated in the device without exceeding ...

  • Page 11

    Production Data CLASS AB DE-RATING CURVE The de-rating curves shown in Figure 3 are based on a full scale sinusoidal input P [W] 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 Figure 3 Class AB Speaker Power De-Rating ...

  • Page 12

    WM8990 ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, T PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Analogue Input Pin Maximum Signal Levels (LIN1, LIN2, LIN3, ...

  • Page 13

    Production Data Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, T PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Analogue Input Pin Impedances (LIN1, LIN2, LIN3, LIN4, RIN1, RIN2, ...

  • Page 14

    WM8990 Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, T PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Input Programmable Gain Amplifiers (PGAs) LIN12, LIN34, RIN12 and RIN34 C1 ...

  • Page 15

    Production Data Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, T PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER ADC Input Path Performance D1 SNR (A-weighted) THD (-1dBFS input) ...

  • Page 16

    WM8990 Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, T PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER DAC Output Path (Line Outputs 10kΩ / 50pF Load, Headphone Outputs ...

  • Page 17

    Production Data Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, T PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER E7 SNR (A-weighted) THD (P =20mW) O THD+N (P =20mW) ...

  • Page 18

    WM8990 Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, T PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Bypass Path Performance (Line Outputs 10kΩ / 50pF load, Headphone Outputs ...

  • Page 19

    Production Data Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, T PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER F4 SNR (A-weighted) THD (0dB output) THD+N (0dB output) AVDD ...

  • Page 20

    WM8990 Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, T PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Multi-Path Channel Separation G1 Headset Voice Call: DAC/Headset to Tx Voice ...

  • Page 21

    Production Data Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, T PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER G6 Headset Voice Call: Tx Voice and Rx Voice Separation ...

  • Page 22

    WM8990 Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, SPKVDD = 5V, T PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER Analogue Reference Levels H1 VMID Midrail Reference Voltage Microphone Bias H2 ...

  • Page 23

    Production Data TERMINOLOGY 1. Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum theoretical full scale output signal and the output with no input signal applied. 2. Total Harmonic Distortion (dB) – THD ...

  • Page 24

    WM8990 TYPICAL POWER CONSUMPTION Control Register Other settings Mode OFF 01 (default state at power-up OFF 01 (thermal sensor disabled SLEEP 01 (VMID enabled, thermal sensor anabled Stereo Line Record 01 ...

  • Page 25

    Production Data SPEAKER DRIVER PERFORMANCE Typical speaker driver THD+N performance is shown below for both Class D and Class AB modes. Curves are shown for four typical SPKVDD supply voltage and gain combinations. Load R = 8Ω + 10μH, Frequency ...

  • Page 26

    WM8990 PSRR PERFORMANCE SPKVDD – LIN2 to Speaker PSRR - SPKVDD LIN2 to SPK class AB LIN2-SPK (Class SPKVDD 10 LIN2-SPK (Class AB SPKVDD 0 0.1 1 ...

  • Page 27

    Production Data DCVDD – Line-In to ADC PSRR - DCVDD Line-In to ADC IN2-INMIX-ADC - 3.3V DCVDD 10 IN2-INMIX-ADC - 2.0V DCVDD 0 0.1 1 Frequency (kHz) HPVDD – IN1 Bypass PSRR ...

  • Page 28

    WM8990 AUDIO SIGNAL PATHS - CSB/ADDR SDIN SCLK MODE MCLK GPIO5/DACDAT2 GPIO4/DACLRC2 GPIO3/BCLK2 ADCLRC/GPIO1 ADCDAT DACDAT DACLRC BCLK DGND DCVDD DBVDD HPVDD HPGND SPKVDD SPKGND AVDD VMID AGND PD, March 2009, Rev 4.0 Production Data 28 ...

  • Page 29

    Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 4 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=3.3V, SPKVDD=5V, DGND=AGND=SPKGND=0V, T PARAMETER System Clock Timing Information MCLK cycle time MCLK duty cycle w t MCLKL t MCLKH t MCLKY ...

  • Page 30

    WM8990 AUDIO INTERFACE TIMING – MASTER MODE Figure 5 Digital Audio Data Timing - Master Mode (see Control Interface) Test Conditions DCVDD=1.8V, DBVDD=AVDD=3.3V, SPKVDD=5V, DGND=AGND=SPKGND=0V, T MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Timing Information ADCLRC/ DACLRC (or ...

  • Page 31

    Production Data AUDIO INTERFACE TIMING – SLAVE MODE Figure 6 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=3.3V, SPKVDD=5V, DGND=AGND=SPKGND=0V, T MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information BCLK (or BCLK2) cycle ...

  • Page 32

    WM8990 AUDIO INTERFACE TIMING – TDM MODE In TDM mode important that two ADC devices to not attempt to drive the ADCDAT pin simultaneously. The timing of the WM8990 ADCDAT tri-stating at the start and end of the ...

  • Page 33

    Production Data CONTROL INTERFACE TIMING – 2-WIRE MODE 2-wire mode is selected by connecting the MODE pin low. SDIN SCLK Figure 8 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=HPVDD=3.3V, SPKVDD=5V, DGND=AGND=HPGND=SPKGND=0V, T fs=48kHz, MCLK = ...

  • Page 34

    WM8990 CONTROL INTERFACE TIMING – 3-WIRE MODE 3-wire mode is selected by connecting the MODE pin high. Figure 9 Control Interface Timing – 3-Wire Serial Control Mode (Write Cycle) CSB SCLK SDOUT Figure 10 Control Interface Timing – 3-Wire Serial ...

  • Page 35

    Production Data CONTROL INTERFACE TIMING – 4-WIRE MODE 4-wire mode supports readback via SDOUT which is available as a GPIO pin function. Figure 11 Control Interface Timing – 4-Wire Serial Control Mode (Write Cycle) CSB SCLK SDOUT Figure 12 Control ...

  • Page 36

    WM8990 INTERNAL POWER ON RESET CIRCUIT Figure 13 Internal Power on Reset Circuit Schematic The WM8990 includes an internal Power-On-Reset Circuit, as shown in Figure 13, which is used to reset the digital logic into a default state after power ...

  • Page 37

    Production Data Figure 15 Typical Power up Sequence where DCVDD is Powered before AVDD Figure 15 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that DCVDD is already up to specified operating voltage. When ...

  • Page 38

    WM8990 DEVICE DESCRIPTION INTRODUCTION The WM8990 is a low power, high quality audio codec designed to interface with a wide range of processors and analogue components. A high level of mixed-signal integration in a very small 3.226x3.44mm footprint makes it ...

  • Page 39

    Production Data INPUT SIGNAL PATH The WM8990 has eight highly flexible analogue input channels, configurable in many combinations of the following four pseudo-differential or single-ended microphone inputs eight mono line inputs or 4 stereo ...

  • Page 40

    WM8990 MICROPHONE INPUTS Up to four microphones can be connected to the WM8990, either in single-ended or pseudo- differential mode. A low noise microphone bias is fully integrated to reduce the need for external components. In single-ended microphone input configuration, ...

  • Page 41

    Production Data Figure 19 LIN1 or RIN1 as Line Inputs Figure 21 LIN3 or RIN3 as Line Inputs Figure 23 LIN4 and RIN4 as RX Voice Inputs with Direct Low Power Path to Ear Speaker w WM8990 Figure 20 LIN2 ...

  • Page 42

    WM8990 Figure 24 LIN4 or RIN4 as Line Inputs INPUT PGA ENABLE The Input PGAs are enabled using register bits LIN12_ENA, LIN34_ENA, RIN12_ENA and RIN34_ENA as described in Table 2. REGISTER ADDRESS R2 (02h) Table 2 Input PGA Enable To ...

  • Page 43

    Production Data MICROPHONE BIAS CONTROL The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones via an external resistor. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be enabled ...

  • Page 44

    WM8990 INPUT PGA CONFIGURATION Each of the four Input PGAs can be configured in single-ended or pseudo-differential mode. Single-ended microphone operation of an Input PGA is selected by connecting the input source to the inverting PGA input. The non-inverting PGA ...

  • Page 45

    Production Data INPUT PGA VOLUME CONTROL Each of the four Input PGAs has an independently controlled gain range of -16.5dB to +30dB in 1.5dB steps. The gains on the inverting and non-inverting inputs to the PGAs are always equal. Each ...

  • Page 46

    WM8990 R27 (1Bh) Table 5 Input PGA Volume Control w 4:0 RIN12VOL 01011b [4:0] (0dB) 8 IPVU[3] N/A 7 RI34MUTE 1b 6 RI34ZC 0b 4:0 RIN34VOL 01011b [4:0] (0dB) Production Data RIN12 Volume (See Table 6 for volume range) Input ...

  • Page 47

    Production Data LIN12VOL[4:0], LIN34VOL[4:0], RIN12VOL[4:0], RIN34VOL[4:0] Table 6 Input PGA Volume Range w VOLUME (DB) 00000 -16.5 00001 -15.0 00010 -13.5 00011 -12.0 00100 -10.5 00101 -9.0 00110 -7.5 00111 -6.0 01000 -4.5 01001 -3.0 01010 -1.5 01011 0 01100 ...

  • Page 48

    WM8990 INPUT MIXER ENABLE The WM8990 has two analogue input mixers which allow the Input PGAs and Line Inputs to be combined in a number of ways and output to the ADCs or to the Output Mixers via bypass paths. ...

  • Page 49

    Production Data In Mixer Mode (AINLMODE=00, AINRMODE=00), adjustable gain control is available on the input mixers INMIXL and INMIXR for all available input signals (PGA outputs, line inputs and record paths). This configuration is illustrated in Figure 25. The applicable ...

  • Page 50

    WM8990 In Rx Voice Mode (AINLMODE=01, AINRMODE=01), adjustable gain control is available for the RXVOICE output by use of the LR4BVOL[2:0] and LL4BVOL[2:0] register fields on the left channel and by RL4BVOL[2:0] and RR4BVOL[2:0] on the right channel. Both Volume ...

  • Page 51

    Production Data In Differential Mode (AINLMODE=10, AINRMODE=10), no additional volume control is available in the input signal path, but the Input PGA volume control can be used to adjust the signal level as with other modes. Both PGAs on the ...

  • Page 52

    WM8990 INPUT MIXER VOLUME CONTROL The Input Mixer volume controls are described in Table 12 for the Left Channel and Table 13 for the Right Channel. The Input PGA levels may be set to Mute, 0dB or 30dB boost. The ...

  • Page 53

    Production Data REGISTER ADDRESS Table 12 Left Input Mixer Volume Control REGISTER ADDRESS R42 (2A) R44 (2Ch) w BIT LABEL DEFAULT 2:0 LL4BVOL 000b RXVOICE to INMIXL Gain and Mute [2:0] (Mute) 000 = Mute 001 = -12dB 010 = ...

  • Page 54

    WM8990 REGISTER ADDRESS Table 13 Right Input Mixer Volume Control ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8990 uses stereo 24-bit, 64x oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high ...

  • Page 55

    Production Data ADC DIGITAL VOLUME CONTROL The output of the ADCs can be digitally amplified or attenuated over a range from -71.625dB to +17.625dB in 0.375dB steps. The volume of each channel can be controlled separately. The gain for a ...

  • Page 56

    WM8990 ADCL_VOL or ADCR_VOL Volume (dB) 0h MUTE 1h -71.625 2h -71.250 3h -70.875 4h -70.500 5h -70.125 6h -69.750 7h -69.375 8h -69.000 9h -68.625 Ah -68.250 Bh -67.875 Ch -67.500 Dh -67.125 Eh -66.750 Fh -66.375 10h -66.000 ...

  • Page 57

    Production Data HIGH PASS FILTER A digital high pass filter is applied by default to the ADC path to remove DC offsets. This filter can also be programmed to remove low frequency noise in voice applications (e.g. wind noise or ...

  • Page 58

    WM8990 DIGITAL MIXING The ADC and DAC data can be combined in various ways to support a range of different usage modes. Data from either of the two ADCs can be routed to either the left or the right channel ...

  • Page 59

    Production Data The polarity of each ADC output signal can be changed under software control using the ADCL_DATINV and ADCR_DATINV register bits. The AIFADCL_SRC and AIFADCR_SRC register bits may be used to select which ADC is used for the left ...

  • Page 60

    WM8990 DAC INTERFACE VOLUME BOOST A digital gain function is available at the audio interface to boost the DAC volume when a small signal is received on DACDAT. This is controlled using register bits DAC_BOOST[1:0]. To prevent clipping at the ...

  • Page 61

    Production Data ADCL_DAC_SVOL or ADCR_DAC_SVOL Table 23 Digital Sidetone Volume w SIDETONE VOLUME 0000 -36 0001 -33 0010 -30 0011 -27 0100 -24 0101 -21 0110 -18 0111 -15 1000 -12 1001 -9 1010 -6 1011 -3 1100 0 1101 ...

  • Page 62

    WM8990 DIGITAL TO ANALOGUE CONVERTER (DAC) The WM8990 DACs receive digital input data from the DACDAT pin and via the digital sidetone path. The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation ...

  • Page 63

    Production Data DACL_VOL or DACR_VOL Volume (dB) 0h MUTE 1h -71.625 2h -71.250 3h -70.875 4h -70.500 5h -70.125 6h -69.750 7h -69.375 8h -69.000 9h -68.625 Ah -68.250 Bh -67.875 Ch -67.500 Dh -67.125 Eh -66.750 Fh -66.375 10h ...

  • Page 64

    WM8990 DAC SOFT MUTE AND SOFT UN-MUTE The WM8990 has a soft mute function which, when enabled, gradually attenuates the volume of the DAC output. When soft mute is disabled, the gain will either gradually ramp back up to the ...

  • Page 65

    Production Data DAC MONO MIX A DAC digital mono-mix mode can be enabled using the DAC_MONO register bit. This mono mix will be output on the enabled DACs. To prevent clipping, a -6dB attenuation is automatically applied to the mono ...

  • Page 66

    WM8990 OUTPUT SIGNAL PATH The WM8990 output routing and mixers provide a high degree of flexibility, allowing operation of many simultaneous signal paths through the device to various analogue outputs. The outputs provide many combinations of headphone, loudspeaker and single-ended ...

  • Page 67

    Production Data OUTPUT SIGNAL PATHS ENABLE The output mixers and drivers can be independently enabled and disabled as described in Table 31. Note that the headphone outputs LOUT and ROUT have dedicated volume controls result, the output PGAs ...

  • Page 68

    WM8990 OUTPUT MIXER CONTROL The Output Mixer volume controls are described in Table 32 for the Left Channel and Table 33 for the Right Channel. The gain of each of analogue input paths may be controlled independently in the range ...

  • Page 69

    Production Data REGISTER ADDRESS R46 (2Eh) R46 (2Eh) R50 (32h) R48 (30h) R46 (2Eh) R48 (30h) R46 (2Eh) R48 (30h) R46 (2Eh) R50 (32h) R46 (2Eh) R50 (32h) R46 (2Eh) Table 33 Right Output Mixer (ROMIX) Volume Control w BIT ...

  • Page 70

    WM8990 VOLUME SETTING Table 34 LOMIX and ROMIX Volume Range OUTPUT SIGNAL PATH VOLUME CONTROL The output drivers LOPGA, ROPGA, LOUT and ROUT can be independently controlled as shown in Table 35 and Table 36. To minimise pop noise it ...

  • Page 71

    Production Data REGISTER ADDRESS R28 (1Ch) R29 (1Dh) Table 35 LOPGA, ROPGA, LOUT and ROUT Volume Control w BIT LABEL DEFAULT 6:0 ROPGAVOL 79h [6:0] (0dB) 8 OPVU[0] N/A 7 LOZC 0b 6:0 LOUTVOL 00h [6:0] (mute) 8 OPVU[1] N/A ...

  • Page 72

    WM8990 LOPGAVOL, ROPGAVOL, LOUTVOL, ROUTVOL or SPKVOL 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah ...

  • Page 73

    Production Data The speaker mixer SPKMIX, the speaker PGA SPKPGA and the outputs SPKN and SPKP are controlled as described in Table 37. Care should be taken to avoid clipping when enabling more than one path to the speaker mixer. ...

  • Page 74

    WM8990 The output mixers OUT3MIX and OUT4MIX and their outputs OUT3 and OUT4 are controlled as described in Table 38. Care should be taken to avoid clipping when enabling more than one path to OUT3 or OUT4. The OUT3ATTN and ...

  • Page 75

    Production Data The output mixers LOPMIX and LONMIX and their outputs LOP and LON are controlled as described in Table 39. Care should be taken to avoid clipping when enabling more than one path to LOP or LON. The LOATTN ...

  • Page 76

    WM8990 The output mixers ROPMIX and RONMIX and their outputs ROP and RON are controlled as described in Table 40. Care should be taken to avoid clipping when enabling more than one path to ROP or RON. The ROATTN attenuation ...

  • Page 77

    Production Data ANALOGUE OUTPUTS The speaker, headphone and line outputs are highly configurable and may be used in many different ways. SPEAKER OUTPUT CONFIGURATIONS The speaker outputs SPKP and SPKN are driven by the speaker mixer SPKMIX, and speaker volume ...

  • Page 78

    WM8990 REGISTER ADDRESS R35 (23h) R37 (25h) Table 41 Speaker Boost Control HEADPHONE OUTPUT CONFIGURATIONS The headphone outputs LOUT, ROUT, OUT3 and OUT4 are each driven by different output mixers as described below. The LOUT and ROUT pins output the ...

  • Page 79

    Production Data When driving a handset ear speaker using OUT3 and OUT4 other than from RXP/RXN, the required phase difference can be provided by inverting one of the DAC outputs or alternatively by mixing Left and Right channels together using ...

  • Page 80

    WM8990 LINE OUTPUT CONFIGURATIONS The line outputs LON, LOP, RON and ROP are each driven by different output mixers as described below. The LOP and ROP pins output a mix of LIN12 input PGA, RIN12 input PGA and either LOMIX ...

  • Page 81

    Production Data Some example line output configurations are shown below. Figure 36 Stereo Line Out (A) Figure 38 Stereo Line Out (B) Figure 40 Stereo Line Out (C) w WM8990 Figure 37 Differential Output of MIC PGA Figure 39 Differential ...

  • Page 82

    WM8990 DISABLED OUTPUTS Whenever an analogue output is disabled, it can be connected to VREF through a resistor; this feature is enabled by setting the BUFIOEN bit – see “Pop Suppression Control”. This helps to prevent pop noise when the ...

  • Page 83

    Production Data GENERAL PURPOSE INPUT/OUTPUT The WM8990 provides a number of versatile GPIO functions to enable features such as mobile TV support, Wi-Fi voice call recording, button and accessory detection and clock output. The WM8990 has six multi-purpose pins for ...

  • Page 84

    WM8990 GPIO CONTROL REGISTERS Table 45 shows how the dual-function GPIO pins are configured to operate in their different modes. Note that the order of precedence described earlier applies. Register field AIF_SEL selects the function of GPIO3, GPIO4 and GPIO5 ...

  • Page 85

    Production Data REGISTER ADDRESS R19 (13h) R20 (14h) R21 (15h) R22 (16h) Table 46 GPIO and GPI Control w BIT LABEL DEFAULT 7 GPIO1_DEB_ENA 0b 6 GPIO1_IRQ_ENA 0b 5 GPIO1_PU 0b 4 GPIO1_PD 0b 3:0 GPIO1_SEL[3:0] 0000b 15 GPIO4_DEB_ENA 0b ...

  • Page 86

    WM8990 The following table describes the coding of the fields listed in Table 46. REGISTER ADDRESS Registers R19 (13h) to R21 (15h) (See Table 46) Table 47 GPIO Function Control Bits The polarity of GPIO/GPI inputs may be configured using ...

  • Page 87

    Production Data ALTERNATIVE DAC INTERFACE The WM8990 may be configured to select between two different audio interfaces, providing the capability to receive DAC input data via BCLK2, DACLRC2 and DACDAT2 instead of BCLK, DACLRC and DACDAT. This selection is made ...

  • Page 88

    WM8990 BUTTON CONTROL The WM8990 GPIO supports button control detection with full status readback for up to seven inputs (and one IRQ output). All inputs are latched at the IRQ Register, with de-bounce available for normal operation. De-bouncing may be ...

  • Page 89

    Production Data MICBIAS CURRENT AND ACCESSORY DETECT A MICBIAS current detect function is provided for accessory detection. When a microphone current is detected (e.g. when a headset is inserted), an interrupt event can be generated and the microphone status read ...

  • Page 90

    WM8990 REGISTER ADDRESS R22 (16h) Table 49 MICBIAS Current Detect Control The current detect function operates according to the following the truth table: Mic Short Circuit Detect Mic Short Circuit Detect Mic Current Detect Mic Current Detect Table 50 Truth ...

  • Page 91

    Production Data TEMPERATURE SENSOR OUTPUT The WM8990 output drivers can generate a large amount of heat. To protect the device from overheating a thermal shutdown function is provided (see "Thermal Shutdown" section for more information). The polarity of the Thermal ...

  • Page 92

    WM8990 PLL LOCK OUTPUT An internal signal used to indicate the lock status of the PLL can be output to a GPIO pin or used to trigger an Interrupt event. The polarity of the PLL Lock indication may be controlled ...

  • Page 93

    Production Data INTERRUPT EVENT OUTPUT An interrupt can be generated by any of the following events described earlier: • • • • The interrupt status flag IRQ is asserted when any un-masked Interrupt input is asserted the OR’d ...

  • Page 94

    WM8990 The IRQ register (R18) is described in Table 55. REGISTER ADDRESS R18 (12h) R23 (17h) GPIO Control (2) Table 55 GPIO Interrupt and Status Readback w BIT LABEL DEFAULT 12 IRQ Read Only (ro) 11 TEMPOK Read or Reset ...

  • Page 95

    Production Data SERIAL DATA OUTPUT (REGISTER READBACK) The GPIO pins can be configured to output serial data during register readback in 3-wire (open-drain) or 4-wire mode. The readback mode is configured using the register bits RD_3W_ENA and MODE_3W4W as described ...

  • Page 96

    WM8990 GPIO SUMMARY The GPIO functions are summarised in Figure 44. Figure 44 GPIO Control Diagram w Production Data PD, March 2009, Rev 4.0 96 ...

  • Page 97

    Production Data Details of the GPIO implementation are shown below. In order to avoid GPIO loops if a GPIO is configured as an output the corresponding input is disabled, as shown in Figure 45 below. Figure 45 GPIO Pad The ...

  • Page 98

    WM8990 The GPIO input or internal Interrupt event (eg. MICBIAS current detect) is latched as illustrated below: Figure 47 GPIO Latch The de-bounce function on the GPIO input pins enables transient behaviour to be filtered as illustrated below: Figure 48 ...

  • Page 99

    Production Data GPIO IRQ HANDLING In the following diagram Figure 50 a typical IRQ scenario is illustrated. Figure 50 GPIO IRQ Handling w WM8990 PD, March 2009, Rev 4.0 99 ...

  • Page 100

    WM8990 DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting DAC data to the WM8990 and outputting ADC data from it. It uses five pins: • • • • • The clock signals BCLK, ADCLRC and DACLRC can ...

  • Page 101

    Production Data Figure 53 Master Mode with ADCLRC as GPIO OPERATION WITH ALTERNATIVE DAC INTERFACE To allow data to be input to the WM8990 DACs from two separate sources, the GPIO[5:3] pins can be configured as an alternative DAC interface ...

  • Page 102

    WM8990 Figure 59 Interface 1 = Slave, Interface 2 = Master The dual Audio Interface approach of the WM8990 has been implemented in such a way that it gives the user and application as much flexibility as possible, without any ...

  • Page 103

    Production Data Figure 61 Audio Interface Input Flow The Audio Interface input flow illustrated above is controlled by only two signals. These are ALRCGPIO1 and AIF_SEL. REGISTER ADDRESS R8 (08h) R9 (09h) Table 57 Audio Interface Pin Function Select w ...

  • Page 104

    WM8990 SYSCLK enable BCLK Generator enable ADCLRC Generator enable DACLRC Generator Figure 62 Audio Interface Output Control The Audio Interface output control is illustrated above. The master mode control registers AIF_MSTR1 and AIF_MSTR2 as well as the left-right clock control ...

  • Page 105

    Production Data These registers are described in Table 58 below. REGISTER ADDRESS R8 (08h) R9 (09h) Table 58 Audio Interface Output Function Control OPERATION WITH TDM Time division multiplexing (TDM) allows multiple devices to transfer data simultaneously on the same ...

  • Page 106

    WM8990 Figure 65 TDM with Processor as Master Note: The WM8990 is a 24-bit device. If the user operates the WM8990 in 32-bit mode then the 8 LSBs will be ignored on the receiving side and not driven on the ...

  • Page 107

    Production Data AUDIO DATA FORMATS (NORMAL MODE) In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency ...

  • Page 108

    WM8990 Figure 68 I2S Justified Audio Interface (assuming n-bit word length) In DSP mode, the left channel MSB is available on either the 1 edge of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRC. Right channel data immediately ...

  • Page 109

    Production Data LRCLK BCLK DACDAT / ADCDAT Figure 71 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave) LRC BCLK DACDAT / ADCDAT Figure 72 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave) PCM operation is supported in DSP interface mode. ...

  • Page 110

    WM8990 Figure 73 TDM in Right-Justified Mode Figure 74 TDM in Left-Justified Mode Figure 75 TDM Mode Production Data PD, March 2009, Rev 4.0 110 ...

  • Page 111

    Production Data Figure 76 TDM in DSP Mode A Figure 77 TDM in DSP Mode B w WM8990 PD, March 2009, Rev 4.0 111 ...

  • Page 112

    WM8990 DIGITAL AUDIO INTERFACE CONTROL The register bits controlling audio data format, word length, left/right channel data source and TDM are summarised in Table 59. REGISTER ADDRESS R4 (04h) R5 (05h) Table 59 Audio Data Format Control w BIT LABEL ...

  • Page 113

    Production Data AUDIO INTERFACE OUTPUT AND GPIO TRISTATE Register bit AIF_TRIS can be used to tristate the audio interface and GPIO pins as described in Table 60. All GPIO pins and digital audio interface pins will be tristated by this ...

  • Page 114

    WM8990 REGISTER ADDRESS R8 (08h) R9 (09h) Table 61 Digital Audio Interface Clock Output Control w BIT LABEL DEFAULT 15 AIF_MSTR1 0b 14 AIF_MSTR2 0b 13 AIF_SEL 0b 11 ADCLRC_DIR 0b 10:0 ADCLRC_RATE 040h [10:0] 15 ALRCGPIO1 0b 11 DACLRC_DIR ...

  • Page 115

    Production Data COMPANDING The WM8990 supports A-law and μ-law companding on both transmit (ADC) and receive (DAC) sides as shown in Table 62. REGISTER ADDRESS R5 (05h) Table 62 Companding Control Companding involves using a piecewise linear approximation of the ...

  • Page 116

    WM8990 Figure 79 μ-Law Companding 120 100 Figure 80 A-Law Companding w u-law Companding 120 100 0.1 0.2 0.3 0.4 Normalised Input A-law Companding 0.2 0.4 Normalised Input ...

  • Page 117

    Production Data LOOPBACK Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data from the ADC audio interface is fed directly into the DAC data input. REGISTER ADDRESS R5 (05h) Table 64 Loopback Control ...

  • Page 118

    WM8990 CLOCKING AND SAMPLE RATES The internal clocks for the ADCs, DACs, DSP core functions, digital audio interface and Class D switching amplifier are all derived from a common internal clock source, SYSCLK. SYSCLK can either be derived directly from ...

  • Page 119

    Production Data SYSCLK CONTROL MCLK may be inverted by setting register bit MCLK_INV. Note that it is not recommended to change the control bit MCLK_INV while the WM8990 is processing data as this may lead to clock glitches and signal ...

  • Page 120

    WM8990 In USB mode, the programmable division set by ADC_CLKDIV must ensure that a 272 * ADC Fs clock is generated for the ADC DSP. DAC_CLKDIV must ensure that a 272 * DAC Fs clock is generated for the DAC ...

  • Page 121

    Production Data Table 67 ADC and DAC Sample Rates w SYSCLK ADC / DAC SAMPLE RATE DIVIDER 000 = SYSCLK / 1 001 = SYSCLK / 1.5 010 = SYSCLK / 2 011 = SYSCLK / 3 12.288 MHz 100 ...

  • Page 122

    WM8990 BCLK CONTROL In Master Mode, BCLK is derived from SYSCLK via a programmable division set by BCLK_DIV, as described in Table 68. BCLK_DIV must be set to an appropriate value to ensure that there are sufficient BCLK cycles to ...

  • Page 123

    Production Data CLASS D SWITCHING CLOCK The Class D switching clock is derived from SYSCLK as determined by register field DCLKDIV as described in Table 70. This clock should be set to between 700kHz and 800kHz for optimum performance. The ...

  • Page 124

    WM8990 PLL The integrated PLL can be used to generate SYSCLK for the WM8990 from a wide range of MCLK reference frequencies. The PLL is enabled by the PLL_ENA register bit. If required, the input reference clock can be divided ...

  • Page 125

    Production Data EXAMPLE PLL CALCULATION To generate 12.288MHz SYSCLK from a 12MHz reference clock: There is a fixed divide the PLL output (see Figure 81) followed by a selectable divide the same path. PLL ...

  • Page 126

    WM8990 CONTROL INTERFACE The WM8990 is controlled by writing to its control registers. Readback is available for certain registers, including device ID, power management registers and some GPIO status bits. The control interface can operate as either a 2-, 3- ...

  • Page 127

    Production Data These modes are shown in the section below. Terminology used in the following figures: TERMINOLOGY Table 76 Terminology Figure 82 2-Wire Serial Control Interface (single write) S Device (0) Figure 83 2-Wire Serial Control Interface ...

  • Page 128

    WM8990 3-WIRE / 4-WIRE SERIAL CONTROL MODES The WM8990 is controlled by writing to registers through 4-wire serial control interface. A control word consists of 24 bits. The first bit is the read/write bit (R/W), which is ...

  • Page 129

    Production Data CSB SCLK SDIN R/W SDOUT control register address Figure 87 4-wire Readback (Push 0/1) CSB SCLK SDIN R undriven SDOUT control register address Figure 88 4-wire Readback (wired-OR ...

  • Page 130

    WM8990 POWER MANAGEMENT POWER MANAGEMENT REGISTERS The WM8990 has three control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To minimise pop or click noise important to ...

  • Page 131

    Production Data REGISTER ADDRESS R3 (03h) w BIT LABEL DEFAULT 8 AINR_ENA 0b (rw) 7 LIN34_ENA 0b (rw) 6 LIN12_ENA 0b (rw) 5 RIN34_ENA 0b (rw) 4 RIN12_ENA 0b (rw) 1 ADCL_ENA 0b (rw) 0 ADCR_ENA 0b (rw) 13 LON_ENA ...

  • Page 132

    WM8990 REGISTER ADDRESS Table 79 Power Management CHIP RESET AND ID The device ID can be read back from register 0. Writing to this register will reset the device. REGISTER ADDRESS R0 (00h) Reset / ID Table 80 Chip Reset ...

  • Page 133

    Production Data POP SUPPRESSION CONTROL In normal operation, the analogue circuits in the WM8990 are referenced to VMID (AVDD/2). When this reference voltage is first enabled, it will ramp quickly from AGND to AVDD/2 and, if connected to an active ...

  • Page 134

    WM8990 The register fields associated with soft start control are described in Table 83. REGISTER ADDRESS R57 (39h) Anti-Pop (2) Table 83 Soft Start Control DISABLED INPUT/OUTPUT CONTROL After start-up, it may be desirable to disable an output stage, in ...

  • Page 135

    Production Data REGISTER ADDRESS R56 (38h) Anti-Pop (1) Table 85 Output Discharge Control VMID REFERENCE DISCHARGE CONTROL The VMID reference can be discharged to AGND through internal resistors. Discharging VMID ensures that a subsequent start-up procedure commences with a known ...

  • Page 136

    WM8990 EXAMPLE CONTROL SEQUENCES Pop-suppression control sequences are described below for typical WM8990 operations involving start-up, muting and disabling of signal paths. Note that these descriptions are intended for guidance only. Application software should be verified and tailored to ensure ...

  • Page 137

    Production Data Shut-down and discharge sequence The following sequence describes the register settings required to mute, disable and discharge the headphone outputs LOUT and ROUT. It assumes that the soft start control and voltage source is already disabled. STEP 1 ...

  • Page 138

    WM8990 POWER DOMAINS Figure 89 WM8990 Power Domains w Production Data PD, March 2009, Rev 4.0 138 ...

  • Page 139

    Production Data REGISTER MAP w WM8990 PD, March 2009, Rev 4.0 139 ...

  • Page 140

    WM8990 Note: A bin default value of ‘p’ indicates a register field where a default value is not applicable e.g. a volume update bit. w Production Data PD, March 2009, Rev 4.0 140 ...

  • Page 141

    Production Data REGISTER BITS BY ADDRESS REGISTER BIT LABEL ADDRESS R0 (00h) 15:0 SW_RESET_CHIP_ ID Reset / ID [15:0] (rr) R1 (01h) 15:13 Power 12 SPK_ENA Management (rw) (1) 11 OUT3_ENA (rw) 10 OUT4_ENA (rw) 9 LOUT_ENA (rw) 8 ROUT_ENA ...

  • Page 142

    WM8990 REGISTER BIT LABEL ADDRESS 9 AINL_ENA (rw) 8 AINR_ENA (rw) 7 LIN34_ENA (rw) 6 LIN12_ENA (rw) 5 RIN34_ENA (rw) 4 RIN12_ENA (rw) 3:2 1 ADCL_ENA (rw) 0 ADCR_ENA (rw) R03 (03h) 15:14 Power 13 LON_ENA Management (rw) (3) 12 ...

  • Page 143

    Production Data REGISTER BIT LABEL ADDRESS 5 LOMIX_ENA (rw) 4 ROMIX_ENA (rw) 3:2 1 DACL_ENA (rw) 0 DACR_ENA (rw) R04 (04h) 15 AIFADCL_SRC Audio Interface (1) 14 AIFADCR_SRC 13 AIFADC_TDM 12 AIFADC_TDM_ CHAN 11:9 8 AIF_BCLK_INV 7 AIF_LRCLK_INV 6:5 AIF_WL ...

  • Page 144

    WM8990 REGISTER BIT LABEL ADDRESS 13 AIFDAC_TDM 12 AIFDAC_TDM_ CHAN 11:10 DAC_BOOST [1:0] 9:5 4 DAC_COMP 3 DAC_COMPMODE 2 ADC_COMP 1 ADC_COMPMODE 0 LOOPBACK R06 (06h) 15 TOCLK_RATE Clocking (1) 14 TOCLK_ENA 13 12:9 OPCLKDIV [3:0] w DEFAULT DESCRIPTION 0b ...

  • Page 145

    Production Data REGISTER BIT LABEL ADDRESS 8:6 DCLKDIV [2:0] 5 4:1 BCLK_DIV [3:0] 0 R07 (07h) 15 Clocking (2) 14 SYSCLK_SRC 13 CLK_FORCE 12:11 MCLK_DIV [1:0] 10 MCLK_INV 9:8 w DEFAULT DESCRIPTION 111b Class D Clock Divider 000 = SYSCLK ...

  • Page 146

    WM8990 REGISTER BIT LABEL ADDRESS 7:5 ADC_CLKDIV [2:0] 4:2 DAC_CLKDIV [2:0] 1:0 R08 (08h) 15 AIF_MSTR1 Audio Interface (3) 14 AIF_MSTR2 13 AIF_SEL 12 11 ADCLRC_DIR 10:0 ADCLRC_RATE [10:0] R09 (09h) 15 ALRCGPIO1 Audio Interface ( AIF_TRIS 12 ...

  • Page 147

    Production Data REGISTER BIT LABEL ADDRESS 10:0 DACLRC_RATE [10:0] R10 (0Ah) 15:13 DAC Control 12 DAC_SDMCLK _RATE 11 10 AIF_LRCLKRATE 9 DAC_MONO 8 DAC_SB_FILT 7 DAC_MUTERATE 6 DAC_MUTEMODE 5:4 DEEMP 3 2 DAC_MUTE 1 DACL_DATINV 0 DACR_DATINV R11 (0Bh) 15:9 ...

  • Page 148

    WM8990 REGISTER BIT LABEL ADDRESS Right DAC 8 DAC_VU Digital Volume 7:0 DACR_VOL [7:0] R13 (0Dh) 15:13 Digital 12:9 ADCL_DAC_SVOL Sidetone [3:0] 8:5 ADCR_DAC_SVOL [3:0] 4 3:2 ADC_TO_DACL [1:0] 1:0 ADC_TO_DACR [1:0] R14 (0Eh) 15:9 ADC Control 8 ADC_HPF_ENA 7 ...

  • Page 149

    Production Data REGISTER BIT LABEL ADDRESS R17 (11h) 15:0 R18 (12h) 15:13 GPIO Control 12 IRQ (1) (ro) 11 TEMPOK (rr) 10 MICSHRT (rr) 9 MICDET (rr) 8 PLL_LCK (rr) 7:0 GPIO_STATUS [7:0] (rr) R19 (13h) 15:8 GPIO1 7 GPIO1_DEB_ENA ...

  • Page 150

    WM8990 REGISTER BIT LABEL ADDRESS 3:0 GPIO1_SEL [3:0] R20 (14h) 15 GPIO4_DEB_ENA GPIO3 and GPIO4 14 GPIO4_IRQ_ENA 13 GPIO4_PU 12 GPIO4_PD 11:8 GPIO4_SEL [3:0] 7 GPIO3_DEB_ENA 6 GPIO3_IRQ_ENA 5 GPIO3_PU 4 GPIO3_PD w DEFAULT DESCRIPTION 0000b GPIO1 Function Select 0000 ...

  • Page 151

    Production Data REGISTER BIT LABEL ADDRESS 3:0 GPIO3_SEL [3:0] R21 (15h) 15:8 GPIO5 7 GPIO5_DEB_ENA 6 GPIO5_IRQ_ENA 5 GPIO5_PU 4 GPIO5_PD 3:0 GPIO5_SEL [3:0] R22 (16h) 15 RD_3W_ENA GPI7 and GPI8 14 MODE_3W4W 13:12 11 TEMPOK_IRQ_ENA 10 MICSHRT_IRQ_EN A w ...

  • Page 152

    WM8990 REGISTER BIT LABEL ADDRESS 9 MICDET_IRQ_ENA 8 PLL_LCK_IRQ_ENA 7 GPI8_DEB_ENA 6 GPI8_IRQ_ENA 5 4 GPI8_ENA 3 GPI7_DEB_ENA 2 GPI7_IRQ_ENA 1 0 GPI7_ENA R23 (17h) 15:13 GPIO Control 12 IRQ_INV (2) (rw) 11 TEMPOK_POL (rw) 10 MICSHRT_POL (rw) 9 MICDET_POL ...

  • Page 153

    Production Data REGISTER BIT LABEL ADDRESS LIN12 Input 8 IPVU[0] PGA Volume 7 LI12MUTE 6 LI12ZC 5 4:0 LIN12VOL [4:0] R25 (19h) 15:9 LIN34 Input 8 IPVU[1] PGA Volume 7 LI34MUTE 6 LI34ZC 5 4:0 LIN34VOL [4:0] R26 (1Ah) 15:9 ...

  • Page 154

    WM8990 REGISTER BIT LABEL ADDRESS R28 (1Ch) 15:9 Left 8 OPVU[0] Headphone Output Volume 7 LOZC 6:0 LOUTVOL [6:0] R29 (1Dh) 15:9 Right 8 OPVU[1] Headphone Output Volume 7 ROZC 6:0 ROUTVOL [6:0] R30 (1Eh) 15:7 Line Output 6 LONMUTE ...

  • Page 155

    Production Data REGISTER BIT LABEL ADDRESS LOPGA 8 OPVU[2] Volume 7 LOPGAZC 6:0 LOPGAVOL [6:0] R33 (21h) 15:9 ROPGA 8 OPVU[3] Volume 7 ROPGAZC 6:0 ROPGAVOL [6:0] R34 (22h) 15:2 Speaker 1:0 SPKATTN Volume [1:0] R35 (23h) 15:9 Class D ...

  • Page 156

    WM8990 REGISTER BIT LABEL ADDRESS 6:0 SPKVOL [6:0] R39 (27h) 15:4 Input Mixers 3:2 AINLMODE (1) [1:0] 1:0 AINRMODE [1:0] R40 (28h) 15:8 Input Mixers 7 LMP4 (2) 6 LMN3 5 LMP2 4 LMN1 3 RMP4 2 RMN3 1 RMP2 ...

  • Page 157

    Production Data REGISTER BIT LABEL ADDRESS 2:0 LDBVOL [2:0] R42 (2Ah) 15:9 Input Mixers 8 R34MNB (4) 7 R34MNBST 6 5 R12MNB 4 R12MNBST 3 2:0 RDBVOL [2:0] R43 (2Bh) 15:9 Input Mixers 8:6 LI2BVOL (5) [2:0] 5:3 LR4BVOL [2:0] ...

  • Page 158

    WM8990 REGISTER BIT LABEL ADDRESS 2:0 LL4BVOL [2:0] R44 (2Ch) 15:9 Input Mixers 8:6 RI2BVOL (6) [2:0] 5:3 RL4BVOL [2:0] 2:0 RR4BVOL [2:0] R45 (2Dh) 15:8 Output Mixers 7 LRBLO (1) 6 LLBLO 5 LRI3LO 4 LLI3LO 3 LR12LO w ...

  • Page 159

    Production Data REGISTER BIT LABEL ADDRESS 2 LL12LO 1 0 LDLO R46 (2Eh) 15:8 Output Mixers 7 RLBRO (2) 6 RRBRO 5 RLI3RO 4 RRI3RO 3 RL12RO 2 RR12RO 1 0 RDRO R47 (2Fh) 15:9 Output Mixers 8:6 LLI3LOVOL (3) ...

  • Page 160

    WM8990 REGISTER BIT LABEL ADDRESS Output Mixers 8:6 RLI3ROVOL (6) [2:0] 5:3 RLBROVOL [2:0] 2:0 RRBROVOL [2:0] R51 (33h) 15:9 OUT3 and 8:7 VSEL OUT4 Mixers [1: LI4O3 4 LPGAO3 3:2 1 RI4O4 0 RPGAO4 R52 (34h) 15:7 ...

  • Page 161

    Production Data REGISTER BIT LABEL ADDRESS 4 ROPRON 3 2 RL12ROP 1 RR12ROP 0 RROPGAROP R54 (36h) 15:8 Speaker 7 LB2SPK Output Mixer 6 RB2SPK 5 LI2SPK 4 RI2SPK 3 LOPGASPK 2 ROPGASPK 1 LDSPK 0 RDSPK R55 (37h) 15:1 ...

  • Page 162

    WM8990 REGISTER BIT LABEL ADDRESS 3 DIS_OUT3 2 DIS_OUT4 1 DIS_LOUT 0 DIS_ROUT R57 (39h) 15:7 Anti-Pop (2) 6 SOFTST 5:4 3 BUFIOEN 2 BUFDCOPEN 1 POBCTRL 0 VMIDTOG R58 (3Ah) 15:8 Microphone 7:6 MCDSCTH Bias [1:0] 5:3 MDCTHR [2:0] ...

  • Page 163

    Production Data REGISTER BIT LABEL ADDRESS 0 MBSEL R59 (3Bh) 15:0 R60 (3Ch) 15:8 PLL (1) 7 SDM 6 PRESCALE 5 4 3:0 PLLN [3:0] R61 (3Dh) 15:8 PLL (2) 7:0 PLLK [15:8] R62 (3Eh) 15:8 PLL (3) 7:0 PLLK ...

  • Page 164

    WM8990 DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS ADC Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Normal Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Sloping Stopband Filter Passband Passband Ripple Stopband 1 Stopband 1 Attenuation Stopband 2 Stopband 2 ...

  • Page 165

    Production Data ADC FILTER RESPONSES 20 0 -20 -40 -60 -80 -100 -120 -140 0.00 0.25 0.50 Frequency (fs) Figure 90 ADC Digital Filter Frequency Response ADC HIGH PASS FILTER RESPONSES 2.1246m -1.1717 -2.3455 -3.5193 -4.6931 -5.8669 -7.0407 -8.2145 -9.3883 ...

  • Page 166

    WM8990 DAC FILTER RESPONSES DAC STOPBAND ATTENUATION The DAC digital filter type is selected by the DAC_SB_FILT register bit as shown in Table 91. REGISTER ADDRESS R10 (0Ah) Table 91 DAC Filter Selection MAGNITUDE(dB) 10 -10 0 0.5 1 1.5 ...

  • Page 167

    Production Data DE-EMPHASIS FILTER RESPONSES MAGNITUDE(dB 5000 10000 - -10 Frequency (Hz) Figure 98 De-Emphasis Digital Filter Response (32kHz) MAGNITUDE(dB 5000 10000 15000 - ...

  • Page 168

    WM8990 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS w Production Data PD, March 2009, Rev 4.0 168 ...

  • Page 169

    Production Data SPEAKER SELECTION For filterless operation important to select a speaker with appropriate internal inductance. The internal inductance and the speaker's load resistance create a low-pass filter with a cut-off frequency of: e.g. for an 8Ω speaker ...

  • Page 170

    WM8990 The distance between the WM8990 and the speakers should be kept to a minimum to reduce series resistance, and also to reduce EMI. Further reductions in EMI can be achieved by additional passive filtering and/or shielding as shown in ...

  • Page 171

    Production Data PACKAGE DIMENSIONS B: 42 BALL W-CSP PACKAGE 3.226 DETAIL 2 BOTTOM VIEW bbb Dimensions (mm) Symbols MIN NOM A ...

  • Page 172

    ... WM8990 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...