WM8990ECS/RV Wolfson Microelectronics, WM8990ECS/RV Datasheet - Page 109

• Manufacturer Part Number: WM8990ECS/RV
• Description: Audio CODECs Stereo CODEC w.Class AB/D speaker driver
• Manufacturer: Wolfson Microelectronics

Specifications of WM8990ECS/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

w
Production Data
Figure 71 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave)
Figure 72 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave)
PCM operation is supported in DSP interface mode. WM8990 ADC data that is output on the Left
Channel will be read as mono PCM data by the receiving equipment. Mono PCM data received by
the WM8990 will be treated as Left Channel data. This data may be routed to the Left/Right DACs as
described in the “Digital Input Path” section.
AUDIO DATA FORMATS (TDM MODE)
TDM is supported in master and slave mode and is enabled by register bits AIF_ADC_TDM and
AIF_DAC_TDM. All audio interface data formats support time division multiplexing (TDM) for ADC
and DAC data.
Two time slots are available (Slot 0 and Slot 1), selected by register bits AIFADC_TDM_CHAN and
AIFDAC_TDM_CHAN which control time slots for the ADC data and the DAC data.
When TDM is enabled, the ADCDAT pin will be tri-stated immediately before and immediately after
data transmission, to allow another ADC device to drive this signal line for the remainder of the
sample period. Note that it is important that two ADC devices do not attempt to drive the data pin
simultaneously. A short circuit may occur if the transmission time of the two ADC devices overlap
with each other. See “Audio Interface Timing - TDM Mode” for details of the ADCDAT output relative
to BCLK signal. Note that it is possible to ensure a gap exists between transmissions by setting the
transmitted word length to a value higher than the actual length of the data. For example, if 32-bit
word length is selected where only 24-bit data is available, then the WM8990 interface will tri-state
after transmission of the 24-bit data, ensuring a gap after the WM8990’s TDM slot.
When TDM is enabled, BCLK frequency must be high enough to allow data from both time slots to
be transferred. The relative timing of Slot 0 and Slot 1 depends upon the selected data format as
shown in Figure 73 to Figure 77.
DACDAT /
DACDAT /
ADCDAT
ADCDAT
LRCLK
BCLK
BCLK
LRC
MSB
1
MSB
1
2
1 BCLK
1 BCLK
2
3
Input Word Length (WL)
LEFT CHANNEL
3
Input Word Length (WL)
LEFT CHANNEL
n-2 n-1
falling edge can occur anywhere in this area
n-2 n-1
LSB
falling edge can occur anywhere in this area
n
LSB
n
1
1
2
2
3
RIGHT CHANNEL
RIGHT CHANNEL
3
1/fs
1/fs
n-2 n-1
n-2 n-1
n
n
PD, March 2009, Rev 4.0
1 BCLK
1 BCLK
WM8990
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