WM8990ECS/RV Wolfson Microelectronics, WM8990ECS/RV Datasheet - Page 118

• Manufacturer Part Number: WM8990ECS/RV
• Description: Audio CODECs Stereo CODEC w.Class AB/D speaker driver
• Manufacturer: Wolfson Microelectronics

Specifications of WM8990ECS/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8990
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CLOCKING AND SAMPLE RATES
The internal clocks for the ADCs, DACs, DSP core functions, digital audio interface and Class D
switching amplifier are all derived from a common internal clock source, SYSCLK.
SYSCLK can either be derived directly from MCLK, or may be generated from a PLL using MCLK as
an external reference. Many commonly-used audio sample rates can be derived directly from typical
MCLK frequencies; the PLL provides additional flexibility for a wide range of MCLK frequencies. All
clock configurations must be set up before enabling playback to avoid glitches.
The ADC and DAC sample rates are independently selectable, relative to SYSCLK, using
ADC_CLKDIV and DAC_CLKDIV. These fields must be set according to the required sampling
frequency and depending on the selected clocking mode (AIF_LRCLKRATE).
In master mode, BCLK is also derived from SYSCLK via a programmable division set by BCLK_DIV.
In the case where the ADCs and DACs are operating at different sample rates, BCLK must be set
according to whichever is the faster rate. The ADCLRC and DACLRC signals do not automatically
match the ADC and DAC sample rates; these must be configured using ADCLRC_RATE and
DACLRC_RATE as described under “Digital Audio Interface Control”.
A clock (OPCLK) derived from SYSCLK can be output on the GPIO pins to provide clocking for other
parts of the system. This clock is enabled by OPCLK_ENA and its frequency is set by OPCLKDIV.
A slow clock (TOCLK) derived from SYSCLK can be used to de-bounce the button/accessory detect
inputs, and to set the timeout period for volume updates when zero-cross detect is used. This clock
is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE.
The Class D switching amplifier requires a clock; this is derived from SYSCLK via a programmable
divider DCLKDIV.
Table 65 to Table 71 show the clocking and sample rate controls for MCLK input, BCLK output (in
master mode), ADCs, DACs, class D outputs and GPIO clock output.
The overall clocking scheme for the WM8990 is illustrated in Figure 81.
Figure 81 Clocking Scheme
PD, March 2009, Rev 4.0
Production Data
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