WM8990ECS/RV Wolfson Microelectronics, WM8990ECS/RV Datasheet - Page 119

• Manufacturer Part Number: WM8990ECS/RV
• Description: Audio CODECs Stereo CODEC w.Class AB/D speaker driver
• Manufacturer: Wolfson Microelectronics

Specifications of WM8990ECS/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

w
Production Data
SYSCLK CONTROL
MCLK may be inverted by setting register bit MCLK_INV. Note that it is not recommended to change
the control bit MCLK_INV while the WM8990 is processing data as this may lead to clock glitches
and signal pop and clicks.
The SYSCLK_SRC bit is used to select the source for SYSCLK. The source may be either MCLK or
the PLL output. The selected source is divided by the SYSCLK pre-divider MCLK_DIV to generate
SYSCLK. The selected source may also be adjusted by the MCLK_DIV divider. These register fields
are described in Table 65. See “PLL” for more details of the Phase Locked Loop clock generator.
The WM8990 supports glitch-free SYSCLK source selection. When both clock sources are running
and SYSCLK_SRC is modified to select one of these clocks, a glitch-free clock transition will take
place. The de-glitching circuit will ensure that the minimum pulse width will be no less than the pulse
width of the faster of the two clock sources.
When the initial clock source is to be disabled before changing to the new clock source, the
CLK_FORCE bit must also be used to force the clock source transition to take place. In this case,
glitch-free operation cannot be guaranteed.
Table 65 MCLK and SYSCLK Control
ADC / DAC SAMPLE RATES
The ADC and DAC sample rates are independently selectable, relative to SYSCLK, by setting the
register fields ADC_CLKDIV and DAC_CLKDIV. These fields must be set according to the SYSCLK
frequency, and according to the selected clocking mode.
Two clocking modes are provided - Normal Mode (AIF_LRCLKRATE = 0) allows selection of the
commonly used sample rates from typical audio system clocking frequencies (eg. 12.288MHz); USB
Mode (AIF_LRCLKRATE = 1) allows many of these sample rates to be generated from a 12MHz
USB clock. Depending on the available clock sources, the USB mode may be used to save power by
supporting 44.1kHz operation without requiring the PLL.
The AIF_LRCLKRATE field must be set as described in Table 66 to ensure correct operation of
internal functions according to the SYSCLK / Fs ratio. Table 67 describes the available sample rates
using four different common MCLK frequencies.
In Normal mode, the programmable division set by ADC_CLKDIV must ensure that a 256 * ADC Fs
clock is generated for the ADC DSP. DAC_CLKDIV must ensure that a 256 * DAC Fs clock is
generated for the DAC DSP.
R7 (07h)
REGISTER
ADDRESS
14
13
12:11
10
BIT
SYSCLK_SRC
CLK_FORCE
MCLK_DIV
[1:0]
MCLK_INV
LABEL
DEFAULT
0b
0b
00b
0b
SYSCLK Source Select
0 = MCLK
1 = PLL output
Forces Clock Source Selection
0 = Existing SYSCLK source (MCLK or
PLL output) must be active when
changing to a new clock source.
1 = Allows existing MCLK source to be
disabled before changing to a new clock
source.
SYSCLK Pre-divider. Clock source
(MCLK or PLL output) will be divided by
this value to generate SYSCLK.
00 = Divide SYSCLK by 1
01 = Reserved
10 = Divide SYSCLK by 2
11 = Reserved
MCLK Invert
0 = Master clock not inverted
1 = Master clock inverted
DESCRIPTION
PD, March 2009, Rev 4.0
WM8990
119