WM8990ECS/RV Wolfson Microelectronics, WM8990ECS/RV Datasheet - Page 124

• Manufacturer Part Number: WM8990ECS/RV
• Description: Audio CODECs Stereo CODEC w.Class AB/D speaker driver
• Manufacturer: Wolfson Microelectronics

Specifications of WM8990ECS/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8990
w
PLL
The integrated PLL can be used to generate SYSCLK for the WM8990 from a wide range of MCLK
reference frequencies. The PLL is enabled by the PLL_ENA register bit. If required, the input
reference clock can be divided by 2 by setting the register bit PRESCALE.
The PLL frequency ratio R is equal to f
by register fields PLLN and PLLK, where PLLN is an integer (LSB = 1) and PLLK is the fractional
portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the field
SDM. De-selection of fractional mode results in lower power consumption.
For PLL stability, input frequencies and divisions must be chosen so that 5 ≤ PLLN ≤ 13. Best
performance is achieved for 7 ≤ N ≤9. Also, the PLL performs best when f
and 100MHz.
If PLLK is regarded as a 16-bit integer (instead of a fractional quantity), then PLLN and PLLK may be
determined as follows:
The PLL Control register settings are described in Table 73.
Table 73 PLL Control
R2 (02h)
R60 (3Ch)
R61 (3Dh)
R62 (3Eh)
REGISTER
ADDRESS
•
•
PLLN = int R
PLLK = int (2
15
7
6
3:0
7:0
7:0
BIT
16
(R - PLLN))
PLL_ENA
(rw)
SDM
PRESCALE
PLLN [3:0]
PLLK [15:8]
PLLK [7:0]
LABEL
2
/f
1
(see Figure 81). This ratio is the real number represented
0
0
0b
8h
31h
26h
DEFAULT
PLL Enable
0 = disabled
1 = enabled
Enable PLL Integer Mode
0 = Integer mode
1 = Fractional mode
Divide MCLK by 2 at PLL input
0 = Divide by 1
1 = Divide by 2
Integer (N) part of PLL frequency ratio.
Fractional (K) part of PLL frequency ratio.
(Most significant bits)
Fractional (K) part of PLL frequency ratio.
(Least significant bits)
DESCRIPTION
PD, March 2009, Rev 4.0
2
is set between 90MHz
Production Data
124