WM8990ECS/RV Wolfson Microelectronics, WM8990ECS/RV Datasheet - Page 144

• Manufacturer Part Number: WM8990ECS/RV
• Description: Audio CODECs Stereo CODEC w.Class AB/D speaker driver
• Manufacturer: Wolfson Microelectronics

Specifications of WM8990ECS/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8990
w
R06 (06h)
Clocking (1)
REGISTER
ADDRESS
13
12
11:10
9:5
4
3
2
1
0
15
14
13
12:9
BIT
AIFDAC_TDM
AIFDAC_TDM_
CHAN
DAC_BOOST
[1:0]
DAC_COMP
DAC_COMPMODE
ADC_COMP
ADC_COMPMODE
LOOPBACK
TOCLK_RATE
TOCLK_ENA
OPCLKDIV
[3:0]
LABEL
0b
0b
00b
0b
0b
0b
0b
0b
0b
0b
0000b
DEFAULT
DAC TDM Enable
0 = Normal DACDAT operation
1 = TDM enabled on DACDAT
DACDAT TDM Channel Select
0 = DACDAT data input on slot 0
1 = DACDAT data input on slot 1
DAC Input Volume Boost
00 = 0dB
01 = +6dB (Input data must not exceed -6dBFS)
10 = +12dB (Input data must not exceed -12dBFS)
11 = +18dB (Input data must not exceed -18dBFS)
Reserved - Do Not Change
DAC Companding Enable
0 = disabled
1 = enabled
DAC Companding Type
0 = μ-law
1 = A-law
ADC Companding Enable
0 = disabled
1 = enabled
ADC Companding Type
0 = μ-law
1 = A-law
Digital Loopback Function
0 = No loopback
1 = Loopback enabled (ADC data output is directly input to
DAC data input).
Note: ADC and DAC left/right clocks must be set to the same
pin when using LOOPBACK function (ALRCGPIO1=1)
Timeout Clock Rate
(Selects clock to be used for volume update timeout and
GPIO input de-bounce)
0 = SYSCLK / 2
1 = SYSCLK / 2
Timeout Clock Enable
(This clock is required for volume update timeout and GPIO
input de-bounce)
0 = disabled
1 = enabled
Reserved - Do Not Change
GPIO Output Clock Divider
0000 = SYSCLK
0001 = SYSCLK / 2
0010 = SYSCLK / 3
0011 = SYSCLK / 4
0100 = SYSCLK / 5.5
0101 = SYSCLK / 6
0110 = SYSCLK / 8
0111 = SYSCLK / 12
1000 = SYSCLK / 16
1001 to 1111 = Reserved
21
19
(Slower Response)
(Faster Response)
DESCRIPTION
PD, March 2009, Rev 4.0
Production Data
144