WM8973LGEFL/RV Wolfson Microelectronics, WM8973LGEFL/RV Datasheet - Page 43

• Manufacturer Part Number: WM8973LGEFL/RV
• Description: Audio CODECs Stereo Codec with H/P Spkr
• Manufacturer: Wolfson Microelectronics

Specifications of WM8973LGEFL/RV

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
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AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised in
Table 34. MS selects audio interface operation in master or slave mode. In Master mode BCLK,
ADCLRC and DACLRC are outputs. The frequency of ADCLRC and DACLRC is set by the sample
rate control bits SR[4:0] and USB. In Slave mode BCLK, ADCLRC and DACLRC are inputs.
Table 34 Audio Data Format Control
Note: Right Justified mode does not support 32-bit data.
AUDIO INTERFACE OUTPUT TRISTATE
Register bit TRI, register 24(18h) bit[3] can be used to tristate the ADCDAT pin and switch ADCLRC,
DACLRC and BCLK to inputs. In Slave mode (MASTER=0) ADCLRC, DACLRC and BCLK are by
default configured as inputs and only ADCDAT will be tri-stated, (see Table 35).
Table 35 Tri-stating the Audio Interface
R24(18h)
Additional
Control (2)
R7 (07h)
Digital Audio
Interface
Format
REGISTER
REGISTER
ADDRESS
ADDRESS
BIT
7
6
5
4
3:2
1:0
BIT
3
LABEL
BCLKINV
MS
LRSWAP
LRP
WL[1:0]
FORMAT[1:0]
TRI
LABEL
DEFAULT
0
0
0
0
0
10
10
DEFAULT
Tristates ADCDAT and switches ADCLRC,
DACLRC and BCLK to inputs.
0 = ADCDAT is an output, ADCLRC, DACLRC
and BCLK are inputs (slave mode) or outputs
(master mode)
1 = ADCDAT is tristated, ADCLRC, DACLRC
and BCLK are inputs
BCLK invert bit (for master and slave
modes)
0 = BCLK not inverted
1 = BCLK inverted
Master / Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Left/Right channel swap
1 = swap left and right DAC data in
audio interface
0 = output left and right data as normal
right, left and i2s modes – LRCLK
polarity
1 = invert LRCLK polarity
0 = normal LRCLK polarity
DSP Mode – mode A/B select
1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)
0 = MSB is available on 2nd BCLK rising
edge after LRC rising edge (mode A)
Audio Data Word Length
11 = 32 bits (see Note)
10 = 24 bits
01 = 20 bits
00 = 16 bits
Audio Data Format Select
11 = DSP Mode
10 = I
01 = Left justified
00 = Right justified
2
S Format
DESCRIPTION
PD Rev 4.2 September 2005
DESCRIPTION
WM8973L
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