WM8900LGEFK/RV

Manufacturer Part NumberWM8900LGEFK/RV
DescriptionAudio CODECs Ultra Low Power Hi-Fi CODEC
ManufacturerWolfson Microelectronics
WM8900LGEFK/RV datasheet
 


Specifications of WM8900LGEFK/RV

Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Ultra Low Power CODEC for Portable Multimedia Applications
Featuring Class G Ground Referenced Headphone Driver
DESCRIPTION
The WM8900 is designed for portable multimedia applications
requiring low power consumption, high performance audio and
a compact form factor. Pop and click optimised ground
referenced headphone amplifiers provide high quality audio
performance and improved bass response whilst also
eliminating bulky headphone capacitors. Headphone amplifier
playback power consumption is minimised by implementing an
efficient class G amplifier powered by adaptive charge pump
technology. Flexible analogue signal routing and digital signal
processing
capabilities
enable
advanced
manipulation for fully featured multimedia applications whilst
minimising power consumption.
Stereo 24bit multi-bit sigma-delta ADCs and DACs are used
with over-sampling digital interpolation and decimation filters.
The master clock can be input directly or generated internally
by an integrated low power FLL. WM8900 operates at
analogue supply voltages down to 2.4v. The digital core can
operate at voltages down to 1.8v to save power. Different
sections of the chip can also be powered down under software
control. The WM8900 is supplied in a very small and thin
5x5x0.55mm QFN package, ideal for use in hand-held and
portable systems
Low power, high performance audio features can be realized
with a minimal set of small form factor external components,
reducing BOM costs and PCB dimensions
WOLFSON MICROELECTRONICS plc
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FEATURES
DAC to HP SNR 97dB (‘A’ weighted, 2.4V)
DAC to HP THD -82dB at 48kHz Fs, 2.4V
ADC SNR 95dB (‘A’ weighted, 3.3V)
ADC THD -84dB at 48kHz Fs, 2.4V
Highly Flexible Input and Output Configuration
-
2 single ended or pseudo differential mic inputs
-
2 stereo line inputs (eg. Line In / FM tuner)
-
Up to +48dB microphone/line input gain
-
Stereo output mixers with -15dB to +6dB gain range;
audio
signal
mixing DAC outputs, line, auxiliary and mic inputs
Class-G Ultra-low Power Headphone Driver
-
Up to 12.4mW per channel output power into 32Ω at 3.3V
-
Up to 6.6mW per channel output power into 32Ω at 2.4V
-
Ground referenced outputs
-
Pop and click suppression circuitry
Soft Mute Control
Low Power Consumption with User Selectable Modes
-
9 mW stereo headphone playback (32Ω)
(AVDD = 2.4V, DCVDD = 1.8V, 48k fs)
-
6 mW stereo headphone playback (32Ω)
(AVDD = 2.4V, DCVDD = 1.8V, 8k fs, quiescent)
-
5 mW bypass mode. Line in to stereo headphone
playback (32Ω) (AVDD = 2.4V, DCVDD = 1.8V)
Low Supply Voltages
-
Analogue: 2.4V to 3.3V
-
Digital core: 1.8V to 3.3V
-
Digital I/O: 1.8V to 3.3V
-
Charge Pump High: 2.4V to 3.3V
-
Charge Pump Low: 1.6V to 3.3V
Low Power FLL
-
Supports MCLK input up to 19.2MHz or DACLRC input
down to 8kHz
TDM Mode – dual data time slots for ADC and DAC
Audio Sample Rates (kHz): 8, 11.025, 16, 22.05, 24, 32,
44.1, 48 generated internally from master clock
5 x 5 x 0.55mm 40 lead QFN package
-25 ºC - +85ºC temperature range
APPLICATIONS
MP3 players
Portable Multimedia Applications
Multimedia Handsets
at
http://www.wolfsonmicro.com/enews/
WM8900
Production Data , August 2008, Rev 4.0
Copyright ©2008 Wolfson Microelectronics plc

WM8900LGEFK/RV Summary of contents

  • Page 1

    ... QFN package • -25 ºC - +85ºC temperature range APPLICATIONS • MP3 players • Portable Multimedia Applications • Multimedia Handsets at http://www.wolfsonmicro.com/enews/ WM8900 Production Data , August 2008, Rev 4.0 Copyright ©2008 Wolfson Microelectronics plc ...

  • Page 2

    WM8900 BLOCK DIAGRAM AUX / LCOM W WM8900 LINPUT3/JD LINPUT2 -12 -> 6dB, 3dB steps, mute -12 to +19dB, 1dB steps + + vmid - 0, 13, 20, LINPUT1 29dB, mute INPUT PGAs 0, 13, 20, RINPUT1 29dB, mute - ...

  • Page 3

    Production Data DESCRIPTION ............................................................................................. 1 FEATURES .................................................................................................. 1 APPLICATIONS ........................................................................................... 1 BLOCK DIAGRAM ....................................................................................... 2 TABLE OF CONTENTS ............................................................................... 3 PIN CONFIGURATION................................................................................. 5 ORDERING INFORMATION ........................................................................ 5 PIN DESCRIPTION ...................................................................................... 6 ABSOLUTE MAXIMUM RATINGS............................................................... 7 RECOMMENDED OPERATING CONDITIONS ........................................... 7 ...

  • Page 4

    WM8900 DIGITAL FILTER CHARACTERISTICS................................................... 106 ADC FILTER RESPONSES .............................................................................107 ADC FILTER RESPONSES .............................................................................107 DAC FILTER RESPONSES .............................................................................107 DE-EMPHASIS FILTER RESPONSES ............................................................108 ADC HIGH PASS FILTER RESPONSES .........................................................109 APPLICATIONS INFORMATION ............................................................. 110 RECOMMENDED PATHS................................................................................110 RECOMMENDED POWER DOWN SEQUENCE .............................................115 IMPORTANT NOTICE ...

  • Page 5

    ... Production Data PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8900LGEFK/V -25°C to +85°C WM8900LGEFK/RV -25°C to +85°C Note: Reel quantity = 3500 Tube quantity = 95 w PACKAGE MOISTURE SENSITIVITY 40-lead QFN (5x5x0.55mm) (Pb-free) 40-lead QFN (5x5x0.55mm) (Pb-free, tape and reel) WM8900 PEAK SOLDERING ...

  • Page 6

    WM8900 PIN DESCRIPTION PIN NO NAME 1 MICBIAS 2 LINPUT1 3 RINPUT1 4 LINPUT2 5 RINPUT2 6 LINPUT3 / JD 7 RINPUT3 / JD 8 MODE / GPIO 9 DBVDD 10 DGND 11 MCLK 12 DCVDD 13 BCLK 14 ADCDAT ...

  • Page 7

    Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical ...

  • Page 8

    WM8900 ELECTRICAL CHARACTERISTICS Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=CPGND=HPGND=0V, AVDD=CPVDDHI=2.4V, CPVDDLO=1.8V; T 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL Analogue Inputs (LINPUT1, RINPUT1, LINPUT2, LINPUT3, RINPUT2, RINPUT3) Full-scale Input Signal Level ...

  • Page 9

    Production Data Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=CPGND=HPGND=0V, AVDD=CPVDDHI=2.4V, CPVDDLO=1.8V; T 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL Input resistance R INPUT1 (Note that input boost and bypass path resistances will ...

  • Page 10

    WM8900 Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=CPGND=HPGND=0V, AVDD=CPVDDHI=2.4V, CPVDDLO=1.8V +25 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL Analogue Inputs (LINPUT1, RINPUT1, LINPUT2, RINPUT2, LINPUT3, RINPUT3) to ADC Out Signal ...

  • Page 11

    Production Data Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=CPGND=HPGND=0V, AVDD=CPVDDHI=2.4V, CPVDDLO=1.8V +25 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL Channel Separation L/RINPUT3 to HP_L / HP_R via bypass path Channel ...

  • Page 12

    WM8900 Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=CPGND=HPGND=0V, AVDD=CPVDDHI=2.4V, CPVDDLO=1.8V +25 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL Input capacitance Input leakage FLL Lock Time Lock See note 3 Reference ...

  • Page 13

    Production Data Notes: 1. The bias conditions are explained in Table 45 on page 12. 2. For a given headphone load expected that the HP_L/HP_R output will begin to clip at 6dB lower amplitude for every 50% reduction ...

  • Page 14

    WM8900 POWER CONSUMPTION MODE AVDD V Headphone Playback DAC to HP playback 3.3 2.2640 32ohm load, quiescent 3.0 2.0490 8kHz sample rate 2.4 1.6240 DAC to HP playback 3.3 2.3720 32ohm load, 0.1mW/channel 3.0 2.1480 8kHz sample rate 2.4 1.7050 ...

  • Page 15

    Production Data DAC TO HEADPHONE POWER CONSUMPTION The following tables detail the DAC to Headphone power consumption differences and SNR differences (where applicable) between 4 different playback conditions and 3 different biasing modes. The biasing modes are detailed in Table ...

  • Page 16

    WM8900 SUPPLIES AVDD MODE V mA 3.30 4.77 1.80 3.00 4.08 1.80 Default mode 2.40 3.03 1.80 2.40 3.11 1.80 3.30 3.28 1.80 Reduced power 3.00 2.73 1.80 mode 2.40 1.96 1.80 2.40 2.05 1.80 3.30 2.82 1.80 Ultra Low ...

  • Page 17

    Production Data Notes: 1. Quiescent power consumption with OUT2VOL = 0dB is slightly higher than would be measured under typical listening levels. The headphone amplifier is being powered by CPVDDHI under quiescent test conditions. During typical playback listening levels (no ...

  • Page 18

    WM8900 EXTERNAL COMPONENTS Figure 1 illustrates the recommended external components for the WM8900. The configuration illustrated shows two pseudo-differential microphone inputs, two line inputs, two line outputs and the ground-referenced headphone output driver. Other configurations may require fewer external components. ...

  • Page 19

    Production Data IDENTIFIER VALUE 4.7 uF C10 1 uF C11 1 uF C12 1 uF ...

  • Page 20

    WM8900 Figure 2 Recommended Filter Connections between WM8900 Audio Outputs and Audio Analyser for Measurement and Testing Only w Production Data PD, August 2008, Rev 4.0 20 ...

  • Page 21

    Production Data AUDIO PATHS OVERVIEW steps 3dB +6dB, to -15 Figure 3 Signal Path Overview and Control Diagram w WM8900 MODE/GPIO CSB/GPIO SDIN SCLK -15 to +6dB, 3dB steps MCLK DACDAT DACLRC ADCDAT ADCLRC/GPIO BCLK AVDD 4.7uF VMID AGND PD, ...

  • Page 22

    WM8900 SYSTEM CLOCK TIMING MCLK Figure 4 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=CPGND=HPGND=0V, AVDD=CPVDDHI=2.4V, CPVDDLO=1.6V; T PARAMETER System Clock Timing Information MCLK cycle time (Codec clocked directly) MCLK cycle time (Codec clocked via FLL) MCLK duty cycle ...

  • Page 23

    Production Data AUDIO INTERFACE TIMING MASTER MODE The Digital Audio Data timing in Master Mode is illustrated in Figure 5. See “Digital Audio Interface” for further details. Figure 5 Digital Audio Data Timing - Master Mode Test Conditions DCVDD=1.8V, DBVDD=1.8V, ...

  • Page 24

    WM8900 SLAVE MODE The Digital Audio Data timing in Slave Mode is illustrated in Figure 6. See “Digital Audio Interface” for further details. Figure 6 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=0V, AVDD=2.4V; T MCLK= ...

  • Page 25

    Production Data CONTROL INTERFACE TIMING 2-WIRE MODE t 3 SDIN t 6 SCLK t 1 Figure 7 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=0V, AVDD=2.4V; T MCLK = 256fs, 24-bit data, unless otherwise stated. ...

  • Page 26

    WM8900 3-WIRE MODE CSB SCLK SDIN Figure 8 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=1.8V, DGND=AGND=0V, AVDD=2.4V; T unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse ...

  • Page 27

    Production Data INTERNAL POWER ON RESET CIRCUIT Figure 9 Internal Power on Reset Circuit Schematic The WM8900 includes an internal Power-On-Reset Circuit, as shown in Figure 9, which is used to reset the digital logic into a default state after ...

  • Page 28

    WM8900 Figure 11 Typical Power up Sequence where DCVDD is Powered before AVDD Figure 11 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that DCVDD is already up to specified operating voltage. When AVDD ...

  • Page 29

    Production Data POP-CLICK MINIMISATION CONTROL REGISTERS It is recommended that the power management control bits are used to enable/disable the required blocks within the WM8900 according to the desired application or mode. The sequencing of these controls may be important ...

  • Page 30

    WM8900 DEVICE DESCRIPTION INTRODUCTION The WM8900 is an ultra low power audio codec offering a combination of high quality audio, advanced features, low power consumption and small package size. These characteristics make it ideal for portable multimedia applications with stereo ...

  • Page 31

    Production Data Rin = 20k / [1/GAIN)+1], where GAIN is voltage gain of the input PGA stage. For example, if the input PGA gain is +13dB, then GAIN = 4.47 and Rin = 16.3k. The external connections for this configuration ...

  • Page 32

    WM8900 Figure 13 Differential Microphone Input Configurations LINE INPUTS • • • Two pairs of stereo line inputs are available as analogue inputs. Each of these may be an internal source (e.g. FM radio IC external signal source. ...

  • Page 33

    Production Data Figure 14 Line Input Configurations Note that when using LRINPUT2 or LRINPUT3, there is inherent feedback signal to LRINPUT1 as shown in Figure 15. Figure 15 Input Feedback INPUT PGA / BOOST MIXER ENABLE The input boost mixers ...

  • Page 34

    WM8900 REGISTER ADDRESS R2 (02h) Power Management 2 Table 10 Input PGA and Boost Mixer Enable Register Settings INPUT PGA CONFIGURATION The input PGAs are configured by the input signal path control registers, as described in Table 11. The input ...

  • Page 35

    Production Data MICROPHONE BIAS The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones via an external resistor. Refer to the Applications Information section for recommended external components. The MICBIAS can be enabled or disabled ...

  • Page 36

    WM8900 REGISTER ADDRESS R22 (16h) Left Input Volume R23 (17h) Right Input Volume Table 14 Input PGA Volume Control See "Volume Updates" for more information on volume update bits, zero cross and timeout operation. See “Headphone Jack Detect” for more ...

  • Page 37

    Production Data REGISTER ADDRESS R26 (1Ah) ADC Signal Path Table 15 Microphone Input PGA Boost Control The boost stage can apply -12dB to +6dB gain to the line inputs. The line inputs may also be muted via the boost gain ...

  • Page 38

    WM8900 ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8900 uses stereo 24-bit, 64x oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduce the effects of jitter and high frequency noise. The ADC Full Scale input level is ...

  • Page 39

    Production Data ADCL_VOL or Volume ADCL_VOL or ADCR_VOL (dB) 0h MUTE 1h -71.625 2h -71.250 3h -70.875 4h -70.500 5h -70.125 6h -69.750 7h -69.375 8h -69.000 9h -68.625 Ah -68.250 Bh -67.875 Ch -67.500 Dh -67.125 Eh -66.750 Fh ...

  • Page 40

    WM8900 ADC DIGITAL FILTERS The ADC filters perform true 24-bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. HIGH PASS FILTER A digital ...

  • Page 41

    Production Data DIGITAL MIXING The ADC and DAC data can be combined in various ways to support a range of different usage modes. Data from either of the two ADCs can be routed to either the left or the right ...

  • Page 42

    WM8900 REGISTER ADDRESS R4 (04h) Audio Interface 1 R14 (0Eh) ADC Control Table 22 ADC Routing and Control The input data source for each DAC can be changed under software control using register bits DACL_SRC and DACR_SRC. The polarity of ...

  • Page 43

    Production Data DIGITAL SIDETONE A digital sidetone is available when ADCs and DACs are operating at the same sample rate. Digital data from either left or right ADC can be mixed with the audio interface data on the left and ...

  • Page 44

    WM8900 DIGITAL TO ANALOGUE CONVERTER (DAC) The WM8900 DACs receive digital input data from the DACDAT pin and via the digital sidetone path. The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation ...

  • Page 45

    Production Data DACL_VOL or Volume DACL_VOL or DACR_VOL (dB) DACR_VOL 0h MUTE 1h -71.625 2h -71.250 3h -70.875 4h -70.500 5h -70.125 6h -69.750 7h -69.375 8h -69.000 9h -68.625 Ah -68.250 Bh -67.875 Ch -67.500 Dh -67.125 Eh -66.750 ...

  • Page 46

    WM8900 DAC SOFT MUTE AND SOFT UN-MUTE The WM8900 has a soft mute and un-mute function, which, when enabled, gradually attenuates or amplifies the volume of the DAC output. When the DAC is un-muted the gain will either gradually ramp ...

  • Page 47

    Production Data REGISTER ADDRESS R10 (0Ah) DAC Control Table 30 DAC Soft-Mute Control DAC MONO MIX A DAC digital mono-mix mode can be enabled using the DAC_MONO register bit. This mono mix will be output on the enabled DACs. To ...

  • Page 48

    WM8900 DAC sample rates. See "Digital Filter Characteristics" section for details of DAC filter characteristics. REGISTER ADDRESS R10 (0Ah) DAC Control Table 33 DAC Sloping Stopband Filter DAC SIGMA-DELTA CLOCK RATE When operating the DAC at lower sample rates (e.g. ...

  • Page 49

    Production Data OUTPUT MIXER CONFIGURATION The output mixers are configured by the output mixer control registers, as described in Table 36. Each mixer input can be independently enabled/disabled. With the exception of the DAC output, each signal’s gain can be ...

  • Page 50

    WM8900 REGISTER ADDRESS R44 (2Ch) Left Output Mixer Control 1 R45 (2Dh) Right Output Mixer Control 1 R46 (2Eh) Bypass 1 w BIT LABEL DEFAULT 8 DACL_TO_MIXOUTL 7 IN3L_TO_MIXOUTL 6:4 IN3L_MIXOUTL_VOL 101 8 DACR_TO_MIXOUTR 7 IN3R_TO_MIXOUTR 6:4 IN3R_MIXOUTR_VOL 101 7 ...

  • Page 51

    Production Data REGISTER ADDRESS R47 (2Fh) Bypass 2 R48 (30h) AUX to Mixer Output Control Table 36 Output Mixer Control w BIT LABEL DEFAULT 7 MIXINR_TO_MIXOUTR 6:4 MIXINR_MIXOUTR_VOL 101 3 MIXINR_TO_MIXOUTL 2:0 MIXINR_MIXOUTL_VOL 101 7 IN4_TO_MIXOUTL 6:4 IN4_MIXOUTL_VOL 101 3 ...

  • Page 52

    WM8900 LINE OUTPUT ENABLE Each analogue output driver can be independently enabled via the Power Management register bits, as described in Table 37. Muting and volume control of the outputs is only possible when the correct power management register bits ...

  • Page 53

    Production Data 4.7uF AUX / LCOM DGND LINPUT3/JD LINPUT2 -12 -> 6dB, 3dB steps, mute -12 to -12 -> 6dB, +19dB, 3dB steps, 1dB steps mute + + vmid - 0, 13, 20, LINPUT1 29dB, mute INPUT PGAs -12 -> ...

  • Page 54

    WM8900 REGISTER ADDRESS R51 (33h) Left OUT1 Control R52 (34h) Right OUT1 Control R3 (03h) Power Management 3 Table 38 LINEOUT_1L/ LINEOUT_1R Volume Control w BIT LABEL DEFAULT 8 OUT1_VU 0 7 OUT1L_ZC 0 6 OUT1L_MUTE 1 5:0 OUT1L_VOL 111001 ...

  • Page 55

    Production Data LINEOUT_2L AND LINEOUT_2R OUTPUTS The outputs LINEOUT_2L and LINEOUT_2R are independently controlled by the register bits described in Table 39. The outputs can be independently muted and the volumes controlled in the range -57dB to +6dB. To allow ...

  • Page 56

    WM8900 ULTRA-LOW POWER GROUND-REFERENCED HEADPHONE OUTPUT The WM8900 headphone amplifier architecture offers highly efficient DAC playback at typical listening levels. A level-shifting charge pump enables the headphone output to be ground referenced, eliminating the need for large DC blocking capacitors ...

  • Page 57

    Production Data REGISTER ADDRESS R3 (03h) Power Management 3 Table 40 Charge Pump Control HEADPHONE AMPLIFIER The Headphone amplifier input (HP_INL / HP_INR) must be coupled to the LINEOUT_2L / LINEOUT_2R via a small DC blocking capacitor as illustrated in ...

  • Page 58

    WM8900 OPTIMAL PLAYBACK POWER CONSUMPTION During DAC to Headphone playback, reduced bias modes are available to optimise power consumption, giving increased battery life with a slight performance trade-off. These modes are selected using the register bits DAC_BIAS (R115 bits 2:1),MIXOUT_BIAS ...

  • Page 59

    Production Data VOLUME UPDATES Volume settings will not be applied to input or output PGAs until a '1' is written to one of the update bits. This is to allow left and right channels to be updated at the same ...

  • Page 60

    WM8900 Figure 23 Volume Update Using Zero Cross Detection If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8900 will automatically update the volume. The volume updates will occur between one and two timeout ...

  • Page 61

    Production Data HEADPHONE JACK DETECT The headphone jack detect feature may be used to automatically control any of the Line outputs and Headphone outputs when a connection is made to a jack socket. Any of the ADCLRC/GPIO, LINPUT3/JD, RINPUT3/JD, MODE/GPIO ...

  • Page 62

    WM8900 REGISTER ADDRESS R7 (07h) Clocking 2 Table 46 Jack Detect Control DISABLED OUTPUTS Whenever an analogue output is disabled, it remains connected to VREF through a resistor. This helps to prevent pop noise when the output is re-enabled. The ...

  • Page 63

    Production Data GENERAL PURPOSE INPUT/OUTPUT The WM8900 has three dual purpose input/output pins which may be configured according to the selected control mode and according to GPIO register settings. The three pins are as follows: • • • Two analogue ...

  • Page 64

    WM8900 DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting DAC data into the WM8900 and outputting ADC data from it. It uses five pins: • • • • • The clock signals BCLK, ADCLRC and DACLRC can ...

  • Page 65

    Production Data BCLK GPIO DACLRC WM8900 CODEC ADCDAT DACDAT Note: The ADC and DAC cannot run at different sample rates in this mode Figure 27 Master Mode with ADCLRC as GPIO The Audio Interface output control is illustrated above. The ...

  • Page 66

    WM8900 WM8900 WM8900 Or similar CODEC Figure 31 TDM with Processor as Master Note: The WM8900 is a 24-bit device. If the user operates the WM8900 in 32-bit mode then the 8 LSBs will be ignored on the receiving side ...

  • Page 67

    Production Data Figure 33 Right Justified Audio Interface (assuming n-bit word length mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are ...

  • Page 68

    WM8900 Figure 35 DSP/PCM Mode Audio Interface (mode A, AIF_LRCLKINV=0, Master) Figure 36 DSP/PCM Mode Audio Interface (mode B, AIF_LRCLKINV =0, Master) Figure 37 DSP/PCM Mode Audio Interface (mode A, AIF_LRCLKINV =0, Slave) w Production Data PD, August 2008, Rev ...

  • Page 69

    Production Data Figure 38 DSP/PCM Mode Audio Interface (mode B, AIF_LRCLKINV =0, Slave) AUDIO DATA FORMATS (TDM MODE) TDM is supported in master and slave mode and is enabled by register bits AIF_ADC_TDM and AIF_DAC_TDM. All audio interface data formats ...

  • Page 70

    WM8900 Figure 40 TDM in Right-Justified Mode Figure 41 TDM in I ADCLRC BCLK ADCDAT Figure 42 TDM in DSP/PCM Mode Mode 1/fs 1 BCLK SLOT0 L SLOT0 R SLOT1 L Production Data SLOT1 R PD, ...

  • Page 71

    Production Data ADCLRC BCLK ADCDAT Figure 43 TDM in DSP/PCM Mode B AUDIO INTERFACE CONTROL The register bits controlling audio format, word length and the TDM parameters are summarised in Table 50. In Master mode BCLK, ADCLRC and DACLRC are ...

  • Page 72

    WM8900 REGISTER ADDRESS R5 (05h) Audio Interface 2 Table 50: Audio Data Format Control Notes 1) AIF_BCLK_INV = 1 is not available in Master Mode (BCLK_DIR = 1). AUDIO INTERFACE OUTPUT TRISTATE The audio interface tri-state feature is controlled by ...

  • Page 73

    Production Data See “Clocking and Sample Rates” for the definition of how the clock frequencies are set. REGISTER ADDRESS R6 (06h) Clocking 1 R8 (08h) Audio Interface 3 R9 (09h) Audio Interface 4 Table 52 Master Clock Controls COMPANDING The ...

  • Page 74

    WM8900 Table 54 8-bit Companded Word Composition 120 100 Figure 44 µ-Law Companding 120 100 Figure 45 A-Law Companding LOOPBACK Setting the LOOPBACK register bit enables digital loopback. When this bit ...

  • Page 75

    Production Data Notes: 1. Master Mode: ADC and DAC left/right clocks must be connected together externally the same frequency and completely synchronised, when using LOOPBACK function (ADCLRC_FN=1) 2. Slave Mode recommended to set ADCLRC_FN = ...

  • Page 76

    WM8900 The overall clocking scheme is illustrated in Figure 46. Figure 46 System Clocking SYSCLK CONTROL The MCLK_SRC bit is used to select the source for SYSCLK. The source may be either MCLK or the output of the FLL. These ...

  • Page 77

    Production Data REGISTER ADDRESS R6 (06h) Clocking 1 Table 56 SYSCLK Control ADC / DAC SAMPLE RATES The ADC and DAC sample rates are independently selectable, relative to SYSCLK, by setting the register fields ADC_CLKDIV and DAC_CLKDIV. These fields must ...

  • Page 78

    WM8900 SYSCLK 12.2880 MHz 11.2896 MHz 12.0000 MHz 2.0480 MHz Table 58 Derivation of Sample Rates in Normal / USB Modes Note that, in USB mode, the ADC / DAC sample rates do not match exactly with the commonly used ...

  • Page 79

    Production Data In Slave Mode, BCLK is generated externally and appears as an input to the CODEC. The host device must provide sufficient BCLK cycles to transfer complete data words to the ADCs and DACs. See “Digital Audio Interface” for ...

  • Page 80

    WM8900 SYSCLK Table 60 BCLK Divider in Master Mode ADCLRC / DACLRC CONTROL In Master Mode, ADCLRC and DACLRC are derived from BCLK via programmable dividers set by ADCLRC_RATE and DACLRC_RATE. The BCLK frequency is derived from SYSCLK according to ...

  • Page 81

    Production Data REGISTER ADDRESS R6 (06h) Clocking 1 Table 62 OPCLK Control SLOWCLK CONTROL A slow clock derived from SYSCLK may be generated for de-bouncing of the headphone detect function or to set the timeout period for volume updates when ...

  • Page 82

    WM8900 When setting up the FLL, after the register write to enable the FLL (FLL_ENA = 1), the FLL output clock will be available after the FLL lock time has elapsed. The FLL lock time is the time from last ...

  • Page 83

    Production Data EXAMPLE FLL SETTINGS Table 65 provides example FLL settings for generating common SYSCLK frequencies from a variety of reference inputs REF OUT VCO 12.000 12.288 98.3040 MHz MHz MHz 12.000 11.289597 90.3168 MHz MHz MHz ...

  • Page 84

    WM8900 CONTROL INTERFACE The WM8900 is controlled by writing to registers through a serial control interface. The interface may be either a 2-wire or 3-wire configuration. SELECTION OF CONTROL MODE At power-up, the MODE pin determines which control mode is ...

  • Page 85

    Production Data The same sequence applies to both Read and Write operations. The only difference is that the data bits are driven by the controlling device in Write mode, and by the WM8900 in Read mode. The R/W bit is ...

  • Page 86

    WM8900 In 2-wire mode, Auto-Incremental Write operations are supported. In this type of transfer, additional bytes of data (B15-B8 and B7-B0) are transmitted in sequence without the need to re-transmit the device address or register address. The WM8900 automatically increments ...

  • Page 87

    Production Data RESETTING THE CHIP The WM8900 can be reset by performing a write of any value to the software reset register (address 00h). This will cause all register values to be reset to their default values. In addition to ...

  • Page 88

    WM8900 REGISTER ADDRESS R3 (03h) Power Management 3 Table 72 Power Management w BIT LABEL DEFAULT 7 OUT1R_ENA 0 5 MIXINL_ENA 0 4 MIXINR_ENA 0 3 INL_ENA 0 2 INR_ENA 0 1 ADCL_ENA 0 0 ADCR_ENA 0 7 CP_ENA 0 ...

  • Page 89

    Production Data STOPPING THE MASTER CLOCK In order to minimise power consumed in the digital core of the WM8900, the master clock may be stopped in Standby and OFF modes. If this cannot be done externally at the clock source, ...

  • Page 90

    WM8900 REGISTER MAP REG NAME RESET (0h) R1 PWR MGMT (1) CHIP_REV[3:0] (1h) R2 PWR MGMT (2) SYSCL 1 0 (2h) K_ENA R3 PWR MGMT ( (3h) R4 AUDIO AIFAD AIFAD AIFAD AIFAD ...

  • Page 91

    Production Data REG NAME (18h) MIXER (1) R25 INPUT BOOST (19h) MIXER (2) R26 ADC SIGNAL (1Ah) PATH R27 AUX BOOST (1Bh) R30 ADDITIONAL (1Eh) ...

  • Page 92

    WM8900 REGISTER ADDRESS BIT R0 (00h) SW_RESET_CHIP_ID 15:0 Reset R1 (01h) 15:12 CHIP_REV [3:0] Power Management 1 8 STARTUP_BIAS_ENA 6 FLL_ENA MICB_ENA 4 3 BIAS_ENA 2 VMID_BUF_ENA VMID_MODE 1:0 [1:0] R2 (02h) 15 SYSCLK_ENA Power Management 2 OUT1L_ENA 8 7 ...

  • Page 93

    Production Data REGISTER ADDRESS BIT ADCR_ENA 0 R3 (03h) 8 OUT1_FB_ENA Power Management 3 7 CP_ENA 6 OUT2L_ENA 5 OUT2R_ENA 3 MIXOUTL_ENA 2 MIXOUTR_ENA 1 DACL_ENA 0 DACR_ENA R4 (04h) AIFADCL_SRC 15 Audio Interface 1 14 AIFADCR_SRC AIFADC_TDM 13 12 ...

  • Page 94

    WM8900 REGISTER ADDRESS BIT AIF_WL 6:5 [1:0] 4:3 AIF_FMT [1:0] R5 (05h) 15 DACL_SRC Audio Interface 2 14 DACR_SRC 13 AIFDAC_TDM AIFDAC_TDM_CHAN 12 11:10 DAC_BOOST [1:0] 6 ADCLRC_FN DAC_COMP 4 DAC_COMPMODE 3 2 ADC_COMP 1 ADC_COMPMODE LOOPBACK 0 w LABEL ...

  • Page 95

    Production Data REGISTER ADDRESS BIT R6 (06h) OPCLK_DIV 14:12 Clocking 1 [2:0] 8 MCLK_SRC 4:1 BCLK_DIV [3:0] 0 BCLK_DIR R7 (07h) AIF_TRI 12 Clocking 2 7:5 ADC_CLKDIV [2:0] w LABEL DEFAULT OPCLK Frequency (GPIO function) 000 000 = SYSCLK 001 ...

  • Page 96

    WM8900 REGISTER ADDRESS BIT DAC_CLKDIV 4:2 [2:0] 1 TOCLK_RATE 0 TOCLK_ENA R8 (08h) 11 ADCLRC_DIR Audio Interface 3 10:0 ADCLRC_RATE [10:0] R9 (09h) DACLRC_DIR 11 Audio Interface 4 10:0 DACLRC_RATE [10:0] R10 (0Ah) 12 DAC_SDMCLK_RATE DAC Control 10 AIF_LRCLKRATE 9 ...

  • Page 97

    Production Data REGISTER ADDRESS BIT DAC_MUTEMODE 6 5:4 DEEMP [1:0] DAC_MUTE 2 1 DACL_DATINV 0 DACR_DATINV R11 (0Bh) 8 DAC_VU Left DAC Digital Volume 7:0 DACL_VOL [7:0] R12 (0Ch) 8 DAC_VU Right DAC Digital Volume 7:0 DACR_VOL [7:0] R13 (0Dh) ...

  • Page 98

    WM8900 REGISTER ADDRESS BIT R14 (0Eh) ADC_HPF_ENA 8 ADC Control 6:5 ADC_HPF_CUT [1:0] 1 ADCL_DATINV 0 ADCR_DATINV R15 (0Fh) 8 ADC_VU Left ADC Digital Volume 7:0 ADCL_VOL [7:0] R16 (10h) 8 ADC_VU Right ADC Digital Volume 7:0 ADCR_VOL [7:0] R17 ...

  • Page 99

    Production Data REGISTER ADDRESS BIT MODE_FN 11 9 JD_ENA 8 JD_MODE ADCLRC_INV 7 6:4 ADCLRC_SRC [2:0] JD_SRC[2:0] 3:1 TEMP_ENA 0 R21 (15h) MICB_LVL 8 Input Control 6 IN1L_ENA IN2L_ENA 5 4 IN3L_ENA IN1R_ENA 2 w LABEL DEFAULT Selects Interface Control ...

  • Page 100

    WM8900 REGISTER ADDRESS BIT IN2R_ENA 1 0 IN3R_ENA R22 (16h) IN_VU 8 Left Input Volume INL_ZC 7 6 INL_MUTE 4:0 INL_VOL [4:0] R23 (17h) IN_VU 8 Right Input Volume INR_ZC 7 6 INR_MUTE INR_VOL 4:0 [4:0] R24 (18h) 6:4 IN3L_BOOST ...

  • Page 101

    Production Data REGISTER ADDRESS BIT R25 (19h) IN3R_BOOST [2:0] 6:4 Input Boost Mixer 2 2:0 IN2R_BOOST [2:0] R26 (1Ah) 6 INL_TO_MIXINL ADC Signal Path 5:4 INL_MIXINL_BOOST [1:0] 2 INR_TO_MIXINR 1:0 INR_MIXINR_BOOST [1:0] R27 (1Bh) 6:4 IN4L_BOOST [2:0] Aux Boost 2:0 ...

  • Page 102

    WM8900 REGISTER ADDRESS BIT VROI 0 R36 (24h) 8 FLL_OSC_ENA FLL Control 1 4:0 FLL_FRATIO [4:0] R37 (25h) 8 FLL_FRACN_ENA FLL Control 2 7:0 FLL_K [15:8] R38 (26h) FLL_K [7:0] 7:0 FLL Control 3 R39 (27h) 4:0 FLL_N [9:5] FLL ...

  • Page 103

    Production Data REGISTER ADDRESS BIT IN3L_MIXOUTL_VOL 6:4 1 DAC_LP DAC_LP_VOL 0 R45 (2Dh) 8 DACR_TO_MIXOUTR Right Output Mixer Control 1 7 IN3R_TO_MIXOUTR IN3R_MIXOUTR_VOL 6:4 R46 (2Eh) MIXINL_TO_MIXOUT 7 L Bypass 1 6:4 MIXINL_MIXOUTL_V OL 3 MIXINL_TO_MIXOUT R MIXINL_MIXOUTR_V 2:0 OL ...

  • Page 104

    WM8900 REGISTER ADDRESS BIT MIXINR_TO_MIXOUT 3 L 2:0 MIXINR_MIXOUTL_V OL R48 (30h) 7 IN4_TO_MIXOUTL AUX to Mixer Output Control 6:4 IN4_MIXOUTL_VOL 3 IN4_TO_MIXOUTR IN4_MIXOUTR_VOL 2:0 R51 (33h) 8 OUT1_VU Left OUT1 Control OUT1L_ZC 7 6 OUT1L_MUTE 5:0 OUT1L_VOL [5:0] R52 ...

  • Page 105

    Production Data REGISTER ADDRESS BIT R53 (35h) OUT2_VU 8 Left OUT2 Control OUT2L_ZC 7 6 OUT2L_MUTE 5:0 OUT2L_VOL [5:0] R54 (36h) 8 OUT2_VU Right OUT2 Control 7 OUT2R_ZC OUT2R_MUTE 6 5:0 OUT2R_VOL [5:0] R58 (3Ah) 7 HP_IPSTAGE_ENA Headphone Control 1 ...

  • Page 106

    WM8900 DIGITAL FILTER CHARACTERISTICS PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Normal Filter Passband Passband Ripple Stopband Stopband Attenuation DAC Sloping Stopband Filter Passband Passband Ripple Stopband 1 Stopband 1 Attenuation Stopband 2 Stopband 2 Attenuation Stopband ...

  • Page 107

    Production Data ADC FILTER RESPONSES 10 -10 -30 -50 -70 -90 -110 -130 -150 Frequency (fs) Figure 50 ADC Digital Filter Frequency Response DAC FILTER RESPONSES MAGNITUDE(dB) 10 -10 0 0.5 1 1.5 -30 -50 -70 -90 -110 -130 -150 ...

  • Page 108

    WM8900 DE-EMPHASIS FILTER RESPONSES MAGNITUDE(dB 5000 10000 - -10 Frequency (Hz) Figure 56 De-Emhpasis Digital Filter Response (32kHz) MAGNITUDE(dB 5000 10000 15000 - ...

  • Page 109

    Production Data ADC HIGH PASS FILTER RESPONSES 2.1246m -1.1717 -2.3455 -3.5193 -4.6931 -5.8669 -7.0407 -8.2145 -9.3883 -10.562 -11.736 1 2.6923 7.2484 19.515 52.54 141.45 380.83 MAGNITUDE(dB) ADC Digital High Pass Filter Frequency Response (48kHz, Hi-Fi Mode, ADC_HPF_CUT[1:0]=00) Figure 62 ADD ...

  • Page 110

    WM8900 APPLICATIONS INFORMATION RECOMMENDED PATHS STEREO DAC TO HEADPHONE The following section details the configuration for stereo DAC to headphone output with charge pump enabled. Slave mode, 24-bit I2S digital audio interface. Block Diagram: Figure 63 Stereo DAC to Headphone ...

  • Page 111

    Production Data REG DATA READ INDEX VALUE OR WRITE 0x35 0x0139 Write OUT2_VU=1, OUT2L_MUTE=0, OUT2L_VOL=11_1001 0x36 0x0139 Write OUT2_VU=1, OUT2R_MUTE=0, OUT2R_VOL=11_1001 0x3A 0x009C Write Set HP_SHORT=1, HP_SHORT2=1, HP_IPSTAGE_ENA=1; Reset CLAMP_IP=0 400ms Delay 0x3A 0x00CC Write Set HP_OPSTAGE_ENA = 1, Reset ...

  • Page 112

    WM8900 Register Settings: REG DATA VALUE READ INDEX OR WRITE 0x1E 0x0102 Set OUT1_DIS=1 (Enable), OUT2_DIS=0 100ms Delay (100ms) to remove any residual charge on LINEOUT_1 Delay 0x01 0x0100 Set STARTUP_BIAS_ENA=1, BIAS_ENA=0 0x1E 0x011A Set BIAS_SRC=1, VMID_SOFTST=1 0x02 0xC180 Set ...

  • Page 113

    Production Data Block diagram: Figure 65 L/RINPUT1 to ADC Internal Signal Path - Recommended Power up Sequence and Device Register Settings Register Settings: REG DATA READ INDEX VALUE OR WRITE R0 0x0000 Write Reset WM8900 R1 0x001D Write Enable VMID, ...

  • Page 114

    WM8900 LINE INPUT 3 TO HEADPHONE (BYPASS PATH) The following section details the configuration for LINPUT3 and RINPUT3 to stereo headphone mode, Note that SYSCLK is still required to operate the charge pump which powers the headphone amplifiers, even although ...

  • Page 115

    Production Data REG DATA READ INDEX VALUE OR WRITE 0x0A 0x1004 Write DAC_SDMCLK_RATE=1, AIF_LRCLKRATE=0, DAC_MONO=0, DAC_SB_FILT=0, DAC_MUTERATE=0, DAC_MUTEMODE=0, DEEMP=00, DAC_MUTE=1, DACL_DATINV=0, DACR_DATINV=0 0x2C 0x00D0 Write DACL_TO_MIXOUTL=0, IN3L_TO_MIXOUTL=1, IN3L_MIXOUTL_VOL=101, DAC_LP=0, DAC_LP_VOL=0 0x2D 0x00D0 Write DACR_TO_MIXOUTR=0, IN3R_TO_MIXOUTR=1, IN3R_MIXOUTR_VOL=101 0x35 0x0139 Write OUT2_VU=1, ...

  • Page 116

    WM8900 PACKAGE DIMENSIONS FL: 40 PIN QFN PLASTIC PACKAGE D2 EXPOSED 6 GND PADDLE (A3 SEATING PLANE Dimensions (mm) Symbols MIN NOM A ...

  • Page 117

    ... Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...