WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 102

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WM8900LGEFK/RV

Manufacturer Part Number
WM8900LGEFK/RV
Description
Audio CODECs Ultra Low Power Hi-Fi CODEC
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM8900LGEFK/RV

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
WM8900LGEFK/RV
Manufacturer:
WOLFSON
Quantity:
20 000
WM8900
w
R36 (24h)
FLL Control 1
R37 (25h)
FLL Control 2
R38 (26h)
FLL Control 3
R39 (27h)
FLL Control 4
R40 (28h)
FLL Control 5
R41 (29h)
FLL Control 6
R44 (2Ch)
Left Output Mixer
Control 1
REGISTER ADDRESS
4:0
7:0
7:0
4:0
8:6
4:0
BIT
0
8
8
8
7
8
7
VROI
FLL_OSC_ENA
FLL_FRATIO
[4:0]
FLL_FRACN_ENA
FLL_K [15:8]
FLL_K [7:0]
FLL_N [9:5]
FLLCLK_DIV
[2:0]
FLL_N [4:0]
FLL_SLOW_LOCK_R
EF
LRCLK_REF_ENA
DACL_TO_MIXOUTL
IN3L_TO_MIXOUTL
LABEL
DEFAULT
0Bh
17h
8h
0h
0h
3h
0
0
0
1
0
0
0
VREF to Analogue Output Resistance
(Disabled Outputs)
0 = 500Ω from buffered VMID to output
1 = 20kΩ from buffered VMID to output
Analogue enable
0 = FLL disabled
1 = FLL enabled
FLL_OSC_ENA must be enabled before
enabling FLL_ENA. The order is important.
CLK_VCO is divided by this integer, valid
from 1 .. 31.
Value 1 recommended for Reference clock
> 96kHz
Value 8 recommended for Reference clock
< 96kHz
Fractional enable
0 = Integer Mode
1 = Fractional Mode
(Fractional N mode increases digital power
consumption of the FLL)
Fractional multiply for CLK_REF
(Most Significant Bits)
Fractional multiply for CLK_REF
(Least Significant Bits)
Integer multiply for CLK_REF
(Most Significant Bits)
F
000 = F
001 = F
010 = F
011 = F
100 = F
101 = Reserved
110 = Reserved
111 = Reserved
Integer multiply for CLK_REF
(Least Significant Bits)
Low frequency reference locking
0 = Lock achieved after 509 ref clks
(Recommended for Reference clock >
48kHz)
1 = Lock achieved after 49 ref clks
(Recommended for Reference clock <=
48kHz)
FLL reference clock input selector
0 = MCLK
1 = DACLRC
Left DAC output to left output mixer
0 = not selected
1 = selected
Left input 3 channel to left output mixer
path
0 = not selected
1 = selected
OUT
clock divider
VCO
VCO
VCO
VCO
VCO
/ 2
/ 4
/ 8 (best performance)
/ 16
/ 32
DESCRIPTION
PD, August 2008, Rev 4.0
Production Data
102

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