WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 115

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
Table 78 LR input 3 to Headphone Bypass Path
Note:
These sequences are optimised for best audio performance and minimal pops; however a faster power up sequence can be
gained by reducing the delay time at the expense of reducing the pop suppression capability of the device
RECOMMENDED POWER DOWN SEQUENCE
Table 79 Recommended Power Down Sequence
Note:
These sequences are optimised for best audio performance and minimal pops; however a faster power up sequence can be
gained by reducing the delay time at the expense of reducing the pop suppression capability of the device.
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INDEX
0x0A
0x2C
0x2D
0x35
0x36
0x3A
0x3A
0x3A
0x3A
0x3A
0x3A
0x3A
0x2C
0x2D
0x01
0x1E
0x01
0x1E
From here, the user can achieve optimal power saving and a predictable mode of operation by writing the default data value
to all registers except R30 (0x1E). These default register writes can be carried out in any order.
INDEX
REG
REG
0x1004
0x00D0
0x00D0
0x0139
0x0139
0x009C
400ms
Delay
0x00CC
0x00C8
0x00C0
0x00C8
0x0088
0x0050
0x0050
0x0109
0x0100
500ms
Delay
0x0100
0x0030
0x001A
VALUE
DATA
VALUE
DATA
WRITE
READ
Write
Write
Write
Write
Write
Write
Write
Write
Write
WRITE
READ
Write
Write
Write
Write
Write
Write
Write
Write
Write
OR
OR
DAC_SDMCLK_RATE=1, AIF_LRCLKRATE=0, DAC_MONO=0, DAC_SB_FILT=0,
DAC_MUTERATE=0, DAC_MUTEMODE=0, DEEMP=00, DAC_MUTE=1,
DACL_DATINV=0, DACR_DATINV=0
DACL_TO_MIXOUTL=0, IN3L_TO_MIXOUTL=1, IN3L_MIXOUTL_VOL=101, DAC_LP=0,
DAC_LP_VOL=0
DACR_TO_MIXOUTR=0, IN3R_TO_MIXOUTR=1, IN3R_MIXOUTR_VOL=101
OUT2_VU=1, OUT2L_ZC=0, OUT2L_MUTE=0, OUT2L_VOL=11_1001
OUT2_VU=1, OUT2R_ZC=0, OUT2R_MUTE=0, OUT2R_VOL=11_1001
HIGHPOW=0, HP_IPSTAGE_ENA=1, HP_OPSTAGE_ENA=0, HP_CLAMP_IP=0,
HP_CLAMP_OP=1, HP_SHORT=1, HP_SHORT2=1, HP_BIAS=00
INSERT_DELAY_MS 400
HIGHPOW=0, HP_IPSTAGE_ENA=1, HP_OPSTAGE_ENA=1, HP_CLAMP_IP=0,
HP_CLAMP_OP=0, HP_SHORT=1, HP_SHORT2=1, HP_BIAS=00
HIGHPOW=0, HP_IPSTAGE_ENA=1, HP_OPSTAGE_ENA=1, HP_CLAMP_IP=0,
HP_CLAMP_OP=0, HP_SHORT=1, HP_SHORT2=0, HP_BIAS=00
HIGHPOW=0, HP_IPSTAGE_ENA=1, HP_OPSTAGE_ENA=1, HP_CLAMP_IP=0,
HP_CLAMP_OP=0, HP_SHORT=0, HP_SHORT2=0, HP_BIAS=00
Set HP_SHORT=1
Reset HP_OPSTAGE_ENA=0
Set CLAMP_IP=1, CLAMP_OP=1; Reset HP_SHORT=0, HP_IPSTAGE_ENA=0
Reset DACL_TO_MIXOUTL=0
Reset DACR_TO_MIXOUTR=0
Set STARTUP_BIAS_ENA=1
Set BIAS_SRC=1, VMID_SOFTST=1
Reset BIAS_ENA=0, VMIDBUF_ENA=0, VMID_MODE=00, Leave
STARTUP_BIAS_ENA=1
INSERT_DELAY_MS [500]
Disable Thermal shutdown, Set OUT1_DIS=1
-
Recommended Power Up Sequence and Device Register Settings
COMMENT
COMMENT
PD, August 2008, Rev 4.0
WM8900
115