WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 28

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8900
Figure 11 Typical Power up Sequence where DCVDD is Powered before AVDD
w
Figure 11 shows a typical power-up sequence where DCVDD comes up first. First it is assumed
that DCVDD is already up to specified operating voltage. When AVDD goes above the minimum
threshold, V
chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD
rises to V
control interface may take place.
On power down, where DCVDD falls first, PORB is asserted low whenever DCVDD drops below
the minimum threshold V
Table 8 Typical POR Operation (typical values, not tested)
Notes:
1.
2.
3.
SYMBOL
V
V
V
V
V
pora_on
pora_off
pord_on
pord_off
If AVDD and DCVDD suffer a brown-out (i.e. drop below the minimum recommended
operating level but do not go below V
resume normal operation when the voltage is back to the recommended level again.
The chip will enter reset at power down when AVDD or DCVDD falls below V
This may be important if the supply is turned on and off frequently by a power management
system.
The minimum t
specification is guaranteed by design rather than test.
pora
pora_on
pora
, PORB is released high and all registers are in their default state and writes to the
, there is enough voltage for the circuit to guarantee PORB is asserted low and the
0.4
0.9
0.4
0.5
0.4
MIN
por
period is maintained even if DCVDD and AVDD have zero rise time. This
0.6
1.2
0.6
0.7
0.6
pord_off
TYP
.
0.8
1.6
0.8
0.9
0.8
MAX
UNIT
V
V
V
V
V
pora_off
or V
pord_off
) then the chip will not reset and will
PD, August 2008, Rev 4.0
Production Data
pora_off
or V
pord_off
28
.