WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 38

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8900
ANALOGUE TO DIGITAL CONVERTER (ADC)
w
The WM8900 uses stereo 24-bit, 64x oversampled sigma-delta ADCs. The use of multi-bit
feedback and high oversampling rates reduce the effects of jitter and high frequency noise. The
ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level
is 1.0V
The ADCs are enabled by the ADCL_ENA/ADCR_ENA register bit.
Table 17 ADC Enable Control
ADC DIGITAL VOLUME CONTROL
The output of the ADCs can be digitally amplified or attenuated over a range from –71.625dB to
+17.625dB in 0.375dB steps. The volume of each channel can be controlled separately. The gain
for a given eight-bit code X is given by:
0.375 × (X-192) dB for 1 ≤ X ≤ 239;
The ADC_VU bit controls the loading of digital volume control data. When ADC_VU is set to 0, the
ADCL_VOL or ADCR_VOL control data will be loaded into the respective control register, but will
not actually change the digital gain setting. Both left and right gain settings are updated when a 1
is written to ADC_VU. This makes it possible to update the gain of both channels simultaneously.
Table 18 ADC Digital Volume Control
R2 (02h)
Power
Management 2
R15 (0Fh)
Left ADC
Digital Volume
R16 (10h)
Right ADC
Digital Volume
REGISTER
ADDRESS
REGISTER
ADDRESS
rms
. Any voltage greater than full scale may overload the ADC and cause distortion.
7:0
7:0
BIT
8
8
BIT
1
0
ADC_VU
ADCL_VOL [7:0]
ADC_VU
ADCR_VOL [7:0]
ADCL_ENA
ADCR_ENA
LABEL
LABEL
MUTE for X = 0
1100 0000
1100 0000
DEFAULT
DEFAULT
(0dB)
(0dB)
0
0
0
0
+17.625dB for 239 ≤ X ≤ 255
ADC Volume Update
Writing a 1 to this bit will cause left
and right ADC volume to be
updated simultaneously
Left ADC Digital Volume
(See Table 19 for volume range)
ADC Volume Update
Writing a 1 to this bit will cause left
and right ADC volume to be
updated simultaneously
Right ADC Digital Volume
(See Table 19 for volume range)
Enable ADC left channel:
0 = ADC disabled
1 = ADC enabled
Enable ADC right channel:
0 = ADC disabled
1 = ADC enabled
PD, August 2008, Rev 4.0
DESCRIPTION
DESCRIPTION
Production Data
38